TL/F/6425
54LS352/DM74LS352
Dual
4-Line
to
1-Line
Data
Selectors/Multiplexers
June 1989
54LS352/DM74LS352 Dual 4-Line to
1-Line Data Selectors/Multiplexers
General Description
Each of these data selectors/multiplexers contains invert-
ers and drivers to supply fully complementary, on-chip, bi-
nary decoding data selection to the AND-OR-invert gates.
Separate strobe inputs are provided for each of the two
four-line sections.
Features
Y
Inverting version of DM54/74LS153
Y
Permits multiplexing from N lines to 1 line
Y
Performs parallel-to-serial conversion
Y
Strobe (enable) line provided for cascading (N lines to
n lines)
Y
High fan-out, low-impedance, totem-pole outputs
Y
Typical average propagation delay times
From data 15 ns
From strobe 19 ns
From select 22 ns
Y
Typical power dissipation 31 mW
Connection Diagram
Dual-In-Line Package
TL/F/6425–1
Order Number 54LS352DMQB, 54LS352FMQB,
DM74LS352M or DM74LS352N
See NS Package Number J16A, M16A, N16E or W16A
Function Table
Select
Data Inputs Strobe Output
Inputs
B A C0 C1 C2 C3 G Y
XXXXXX H H
LL L X X X L H
LL H X X X L L
LH X L X X L H
LH X H X X L L
HL X X L X L H
HL X X H X L L
HH X X X L L H
HH X X X H L L
Select inputs A and B are common to both sections.
H e High Level, L e Low Level, X e Don’t Care
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.