1
D
OUT
ACK
SENSE AMPS
SHIFT REGISTERS
CONTROL
LOGIC
WORD ADDRESS
BUFFERS
START/STOP
LOGIC
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
E
2
PROM
128/256 X 256
V
CC
EXTERNAL LOAD
COLUMN
DECODERS
XDEC
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
V
SS
WP
SCL
A
0
A1
A2
SDA
128/256
256
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A
0
V
CC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A
1
A
2
V
SS
A
0
A
1
A
2
V
SS
DESCRIPTION
The CAT24WC32/64 is a 32K/64K-bit Serial CMOS
E
2
PROM internally organized as 4096/8192 words of 8
bits each. Catalyst’s advanced CMOS technology sub-
stantially reduces device power requirements. The
Preliminary
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
n Zero Standby Current
n Commercial, Industrial and Automotive
Temperature Ranges
n Write Protection
– Entire Array Protected When WP at V
IH
n 1,000,000 Program/Erase Cycles
n 100 Year Data Retention
CAT24WC32/64 features a 32-byte page write buffer.
The device operates via the I
2
C bus serial interface and
is available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION BLOCK DIAGRAM
PIN FUNCTIONS
Pin Name Function
A0, A1, A2 Device Address Inputs
SDA Serial Data/Address
SCL Serial Clock
WP Write Protect
V
CC
+1.8V to +6V Power Supply
V
SS
Ground
24WC32/64 F02
CAT24WC32/64
32K/64K-Bit I
2
C Serial CMOS E
2
PROM
n 400 KHz I
2
C Bus Compatible*
n 1.8 to 6 Volt Read and Write Operation
n Cascadable for up to Eight Devices
n 32-Byte Page Write Buffer
n Self-Timed Write Cycle with Auto-Clear
n 8-Pin DIP or 8-Pin SOIC
n Schmitt Trigger Inputs for Noise Protection
FEATURES
DIP Package (P)
SOIC Package (J,K)
24WC32/64 F01
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25053-00 2/98 S-1