Philips Semiconductors Product specification
TrenchMOS transistor BUK9606-30
Logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effect power transistor in a
plastic envelope suitable for surface V
DS
Drain-source voltage 30 V
mounting using ’trench’ technology. I
D
Drain current (DC) 75 A
Thedevice features verylow on-state P
tot
Total power dissipation 187 W
resistance and has integral zener T
j
Junction temperature 175 ˚C
diodes giving ESD protection up to R
DS(ON)
Drain-source on-state 6 mΩ
2kV. It is intended for use in resistance V
GS
= 5 V
automotive and general purpose
switching applications.
PINNING - SOT404 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
mb drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
Drain-source voltage - - 30 V
V
DGR
Drain-gate voltage R
GS
= 20 kΩ -30
±V
GS
Gate-source voltage - - 10 V
I
D
Drain current (DC) T
mb
= 25 ˚C - 75 A
I
D
Drain current (DC) T
mb
= 100 ˚C - 53 A
I
DM
Drain current (pulse peak value) T
mb
= 25 ˚C - 240 A
P
tot
Total power dissipation T
mb
= 25 ˚C - 187 W
T
stg
, T
j
Storage & operating temperature - - 55 175 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction to - - 0.8 K/W
mounting base
R
th j-a
Thermal resistance junction to minimum footprint, FR4 50 - K/W
ambient board
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
C
Electrostatic discharge capacitor Human body model - 2 kV
voltage, all pins (100 pF, 1.5 kΩ)
d
g
s
13
mb
2
December 1997 1 Rev 1.100