Philips Semiconductors Product specification
TrenchMOS transistor BUK9505-30A
Logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effect power transistor in a
plastic envelope using ’trench’V
DS
Drain-source voltage 30 V
technology which features very low I
D
Drain current (DC) 75 A
on-state resistance. It is intended for P
tot
Total power dissipation 230 W
use in automotive and general T
j
Junction temperature 175 ˚C
purpose switching applications. R
DS(ON)
Drain-source on-state
resistance V
GS
= 5 V 5 mΩ
V
GS
= 10 V 4.6 mΩ
PINNING - TO220AB PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
tab drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
Drain-source voltage - - 30 V
V
DGR
Drain-gate voltage R
GS
= 20 kΩ -30
±V
GS
Gate-source voltage - - 10 V
±V
GSM
Non-repetitive gate-source voltage t
p
≤50µS - 15 V
I
D
Drain current (DC) T
mb
= 25 ˚C - 75 A
I
D
Drain current (DC) T
mb
= 100 ˚C - 75 A
I
DM
Drain current (pulse peak value) T
mb
= 25 ˚C - 400 A
P
tot
Total power dissipation T
mb
= 25 ˚C - 230 W
T
stg
, T
j
Storage & operating temperature - - 55 175 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction to - - 0.65 K/W
mounting base
R
th j-a
Thermal resistance junction to in free air 60 - K/W
ambient
d
g
s
123
tab
August 1999 1 Rev 1.100