Philips Semiconductors Product specification
TrenchMOS transistor BUK7830-30
Standard level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT
standard level field-effect power
transistor in a plastic envelope V
DS
Drain-source voltage 30 V
suitable for surface mounting. Using I
D
Drain current (DC) T
sp
= 25 ˚C 12.8 A
’trench’ technology, the device Drain current (DC) T
amb
= 25 ˚C 5.9 A
features very low on-state resistance P
tot
Total power dissipation 8.3 W
and has integral zener diodes giving T
j
Junction temperature 150 ˚C
ESD protection up to 2kV. It is R
DS(ON)
Drain-source on-state 30 mΩ
intended for use in automotive and resistance V
GS
= 10 V
general purpose switching
applications.
PINNING - SOT223 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
Drain-source voltage - - 30 V
V
DGR
Drain-gate voltage R
GS
= 20 kΩ -30
±V
GS
Gate-source voltage - - 16 V
I
D
Drain current (DC) T
sp
= 25 ˚C - 12.8 A
T
amb
= 25 ˚C - 5.9 A
I
D
Drain current (DC) T
sp
= 100 ˚C - 9 A
T
amb
= 100 ˚C - 4.1 A
I
DM
Drain current (pulse peak value) T
sp
= 25 ˚C - 51.2 A
T
amb
= 25 ˚C - 23.6 A
P
tot
Total power dissipation T
sp
= 25 ˚C - 8.3 W
T
amb
= 25 ˚C - 1.8 W
T
stg
, T
j
Storage & operating temperature - - 55 150 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-sp
Thermal resistance junction to Mounted on any PCB 12 15 K/W
solder point
R
th j-amb
Thermal resistance junction to Mounted on PCB of Fig.19 - 70 K/W
ambient
d
g
s
4
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December 1997 1 Rev 1.100