Philips Semiconductors Product specification
TrenchMOS transistor BUK78150-55
Standard level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effect power transistor in a
plastic envelope suitable for surface V
DS
Drain-source voltage 55 V
mounting. Using ’trench’ technology I
D
Drain current 5.5 A
the device features very low on-state P
tot
Total power dissipation 1.8 W
resistance and has integral zener T
j
Junction temperature 150 ˚C
diodes giving ESD protection. It is R
DS(ON)
Drain-source on-state 150 mΩ
intended for use in automotive and resistance V
GS
= 10 V
general purpose switching
applications.
PINNING - SOT223 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
Drain-source voltage - - 55 V
V
DGR
Drain-gate voltage R
GS
= 20 kΩ -55
±V
GS
Gate-source voltage - - 16 V
I
D
Drain current (DC) T
sp
= 25 ˚C - 5.5 A
I
D
Drain current (DC) On PCB in Fig.19 - 2.6 A
T
amb
= 25 ˚C
I
D
Drain current (DC) On PCB in Fig.19 - 1.6 A
T
amb
= 100 ˚C
I
DM
Drain current (pulse peak value) T
sp
= 25 ˚C - 30 A
P
tot
Total power dissipation T
sp
= 25 ˚C - 8.3 W
P
tot
Total power dissipation On PCB in Fig.19 - 1.8 W
T
amb
= 25 ˚C
T
stg
, T
j
Storage & operating temperature - - 55 150 ˚C
ESD LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
C
Electrostatic discharge capacitor Human body model - 2 kV
voltage (100 pF, 1.5 kΩ)
d
g
s
4
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January 1998 1 Rev 1.000