Philips Semiconductors Product specification
PowerMOS transistor BUK573-48C
Clamped logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
Protected N-channel enhancement SYMBOL PARAMETER MIN. TYP. MAX. UNIT
mode logic level field-effect power
transistor in a plastic full-pack V
(CL)DSR
Drain-source clamp voltage 40 48 58 V
envelope. I
D
Drain current (DC) 13 A
The device is intended for use in P
tot
Total power dissipation 25 W
automotive applications. It has W
DSRR
Repetitive clamped turn off 50 mJ
built-in zener diodes providing active energy; T
j
= 150˚C
drain voltage clamping. R
DS(ON)
Drain-source on-state 85 mΩ
resistance; V
GS
= 5 V
PINNING - SOT186A PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
case isolated
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
Drain-source voltage continuous - 30 V
V
DG
Drain-gate voltage continuous - 30 V
±V
GS
Gate-source voltage - - 15 V
I
D
Drain current (DC) T
hs
= 25 ˚C - 13 A
I
D
Drain current (DC) T
hs
= 100 ˚C - 8.2 A
I
DM
Drain current (pulse peak T
hs
= 25 ˚C - 52 A
value)
P
tot
Total power dissipation T
hs
= 25 ˚C - 25 W
T
stg
Storage temperature - - 55 150 ˚C
T
j
Junction Temperature - - 55 150 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
R
th j-hs
Thermal resistance junction to with heatsink compound - - 5 K/W
heatsink
R
th j-a
Thermal resistance junction to - 55 - K/W
ambient
d
g
s123
case
August 1994 1 Rev 1.000