Philips Semiconductors Product specification
PowerMOS transistor BUK564-200A
Logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effect power transistor in a
plastic envelope suitable for surface V
DS
Drain-source voltage 200 V
mount applications. I
D
Drain current (DC) 9.2 A
The device is intended for use in P
tot
Total power dissipation 90 W
Switched Mode Power Supplies T
j
Junction temperature 175 ˚C
(SMPS), motor control, welding, R
DS(ON)
Drain-source on-state 0.4 Ω
DC/DC and AC/DC converters, and in resistance; V
GS
= 5 V
automotive and general purpose
switching applications.
PINNING - SOT404 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
mb drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
Drain-source voltage - - 200 V
V
DGR
Drain-gate voltage R
GS
= 20 kΩ - 200 V
±V
GS
Gate-source voltage - - 15 V
±V
GSM
Non-repetitive gate-source voltage t
p
≤ 50 µs - 20 V
I
D
Drain current (DC) T
mb
= 25 ˚C - 9.2 A
I
D
Drain current (DC) T
mb
= 100 ˚C - 6.5 A
I
DM
Drain current (pulse peak value) T
mb
= 25 ˚C - 36 A
P
tot
Total power dissipation T
mb
= 25 ˚C - 90 W
T
stg
Storage temperature - - 55 175 ˚C
T
j
Junction temperature - - 175 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction to - - 1.67 K/W
mounting base
R
th j-a
Thermal resistance junction to minimum footprint, - 50 - K/W
ambient FR4 board (see Fig. 18).
13
mb
2
d
g
s
February 1996 1 Rev 1.000