Philips Semiconductors Product specification
PowerMOS transistor BUK563-60A
Logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effect power transistor in
a plastic envelope suitable for V
DS
Drain-source voltage 60 V
surface mount applications. I
D
Drain current (DC) 21 A
The device is intended for use in P
tot
Total power dissipation 75 W
automotive and general purpose T
j
Junction temperature 175 ˚C
switching applications. R
DS(ON)
Drain-source on-state 85 mΩ
resistance V
GS
= 5 V
PINNING - SOT404 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
mb drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
Drain-source voltage - - 60 V
V
DGR
Drain-gate voltage R
GS
= 20 kΩ -60
±
GS
Gate-source voltage - - 15 V
±V
GSM
Non-repetitive gate-source t
p
≤ 50 µs - 20 V
voltage
I
D
Drain current (DC) T
mb
= 25 ˚C - 21 A
I
D
Drain current (DC) T
mb
= 100 ˚C - 15 A
I
DM
Drain current (pulse peak value) T
mb
= 25 ˚C - 84 A
P
tot
Total power dissipation T
mb
= 25 ˚C - 75 W
T
stg
Storage temperature - - 55 175 ˚C
T
j
Junction temperature - - 175 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction to - - 2.0 K/W
mounting base
R
th j-a
Thermal resistance junction to minimum footprint, 50 - K/W
ambient FR4 board (see Fig. 18).
13
mb
2
d
g
s
July 1995 1 Rev 1.000