BUK556-60
器件描述:PowerMOS transistor Logic level FET
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器件资料摘要:
Philips Semiconductors Product Specification
PowerMOS transistor BUK556-60H
Logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effect power transistor in a
plastic envelope. V
DS
Drain-source voltage 60 V
The device is intended for use in I
D
Drain current (DC) 60 A
automotive and general purpose P
tot
Total power dissipation 150 W
switching applications. T
j
Junction temperature 175 ˚C
R
DS(ON)
Drain-source on-state 22 mΩ
resistance; V
GS
= 5 V
PINNING - TO220AB PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
tab drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
Drain-source voltage - - 60 V
V
DGR
Drain-gate voltage R
GS
= 20 kΩ -60
±
GS
Gate-source voltage - - 15 V
I
D
Drain current (DC) T
mb
= 25 ˚C - 60 A
I
D
Drain current (DC) T
mb
= 100 ˚C - 44 A
I
DM
Drain current (pulse peak T
mb
= 25 ˚C - 240 A
value)
P
tot
Total power dissipation T
mb
= 25 ˚C - 150 W
T
stg
Storage temperature - - 55 175 ˚C
T
j
Junction Temperature - - 175 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
R
th j-mb
From junction to mounting base - - 1.0 K/W
R
th j-a
From junction to ambient - 60 - K/W
123
tab
d
g
s
October 1993 1 Rev 1.000