Philips Semiconductors Product Specification
PowerMOS transistor BUK556-60A
Logic level FET
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT
logic level field-effect power
transistor in a plastic envelope. V
DS
Drain-source voltage 60 V
The device is intended for use in I
D
Drain current (DC) 50 A
Switched Mode Power Supplies P
tot
Total power dissipation 150 W
(SMPS), motor control, welding, R
DS(ON)
Drain-source on-state resistance 26 mΩ
DC/DC and AC/DC converters, and V
GS
= 5 V
in automotive and general purpose
switching applications.
PINNING - TO220AB PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
tab drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
Drain-source voltage - - 60 V
V
DGR
Drain-gate voltage R
GS
= 20 kΩ -60
±
GS
Gate-source voltage - - 15 V
±V
GSM
Non-repetitive gate-source voltage t
p
≤ 50 µs - 20 V
I
D
Drain current (DC) T
mb
= 25 ˚C - 50 A
I
D
Drain current (DC) T
mb
= 100 ˚C - 38 A
I
DM
Drain current (pulse peak value) T
mb
= 25 ˚C - 200 A
P
tot
Total power dissipation T
mb
= 25 ˚C - 150 W
T
stg
Storage temperature - - 55 175 ˚C
T
j
Junction Temperature - - 175 ˚C
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction to - - 1.0 K/W
mounting base
R
th j-a
Thermal resistance junction to - 60 - K/W
ambient
123
tab
d
g
s
April 1993 1 Rev 1.100