Philips Semiconductors Product specification
PowerMOS transistor BUK482-200A
GENERAL DESCRIPTION QUICK REFERENCE DATA
N-channel enhancement mode SYMBOL PARAMETER MAX. UNIT
field-effect power transistor in a
plastic envelope suitable for surface V
DS
Drain-source voltage 200 V
mounting featuring high avalanche I
D
Drain current (DC) 2.0 A
energy capability, stable blocking P
tot
Total power dissipation 8.3 W
voltage, fast switching and high R
DS(ON)
Drain-source on-state resistance 0.9 Ω
thermal cycling performance.
Intended for use in Switched Mode
Power Supplies (SMPS) and general
purpose switching applications.
PINNING - SOT223 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 gate
2 drain
3 source
4 drain (tab)
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
Drain-source voltage - 200 V
V
DGR
Drain-gate voltage R
GS
= 20 kΩ - 200 V
±V
GS
Gate-source voltage - 30 V
I
D
Drain current (DC) T
sp
= 25 ˚C - 2.0 A
T
sp
= 100 ˚C - 1.3 A
I
DM
Drain current (pulse peak T
sp
= 25 ˚C - 8.0 A
value)
I
DR
Source-drain diode current T
sp
= 25 ˚C - 2.0 A
(DC)
I
DRM
Source-drain diode current T
sp
= 25 ˚C - 8.0 A
(pulse peak value)
P
tot
Total power dissipation T
sp
= 25 ˚C - 8.3 W
T
stg
Storage temperature -55 150 ˚C
T
j
Junction Temperature - 150 ˚C
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
W
DSS
Drain-source non-repetitive I
D
= 2 A ; V
DD
≤ 50 V ; V
GS
= 10 V ;
unclamped inductive turn-off R
GS
= 50 Ω
energy T
j
= 25˚C prior to surge - 50 mJ
T
j
= 100˚C prior to surge - 8 mJ
4
1 23
d
g
s
January 1998 1 Rev 1.000