BUK113-50DL
器件描述：PowerMOS transistor Logic level TOPFET
器件厂商：PHILIPS [Philips Semiconductors]
文件大小：32.46KB，共6页
Sponsor by e络盟器件资料摘要：
Philips Semiconductors Objective specification
PowerMOS transistor BUK113-50DL
Logic level TOPFET
DESCRIPTION QUICK REFERENCE DATA
Monolithic overload protected logic SYMBOL PARAMETER MIN. MAX. UNIT
level power MOSFET in a surface
mount plastic envelope, intended as V
DS
Continuous drain source voltage - 50 V
a general purpose switch for
automotive systems and other I
D
Drain current limiting 4 8 A
applications.
P
D
Total power dissipation - 4 W
APPLICATIONS
T
j
Continuous junction temperature - 150 ˚C
General controller for driving
lamps R
DS(ON)
Drain-source on-state resistance - 200 mΩ
small motors
solenoids
FEATURES FUNCTIONAL BLOCK DIAGRAM
Vertical power DMOS output
stage
Overload protected up to
125˚C ambient
Overload protection by current
limiting and overtemperature
sensing
Latched overload protection
reset by input
5 V logic compatible input level
Control of power MOSFET
and supply of overload
protection circuits
derived from input
Low operating input current
permits direct drive by
micro-controller
ESD protection on all pins
Overvoltage clamping for turn
off of inductive loads
Fig.1. Elements of the TOPFET.
PINNING - SOT223 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 input
2 drain
3 source
4 drain (tab)
POWER
MOSFET
DRAIN
SOURCE
INPUT
O/V
CLAMP
LOGIC AND
PROTECTION
RIG
4
1 23
P
D
S
I
TOPFET
January 1996 1 Rev 1.000
PowerMOS transistor BUK113-50DL
Logic level TOPFET
DESCRIPTION QUICK REFERENCE DATA
Monolithic overload protected logic SYMBOL PARAMETER MIN. MAX. UNIT
level power MOSFET in a surface
mount plastic envelope, intended as V
DS
Continuous drain source voltage - 50 V
a general purpose switch for
automotive systems and other I
D
Drain current limiting 4 8 A
applications.
P
D
Total power dissipation - 4 W
APPLICATIONS
T
j
Continuous junction temperature - 150 ˚C
General controller for driving
lamps R
DS(ON)
Drain-source on-state resistance - 200 mΩ
small motors
solenoids
FEATURES FUNCTIONAL BLOCK DIAGRAM
Vertical power DMOS output
stage
Overload protected up to
125˚C ambient
Overload protection by current
limiting and overtemperature
sensing
Latched overload protection
reset by input
5 V logic compatible input level
Control of power MOSFET
and supply of overload
protection circuits
derived from input
Low operating input current
permits direct drive by
micro-controller
ESD protection on all pins
Overvoltage clamping for turn
off of inductive loads
Fig.1. Elements of the TOPFET.
PINNING - SOT223 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION
1 input
2 drain
3 source
4 drain (tab)
POWER
MOSFET
DRAIN
SOURCE
INPUT
O/V
CLAMP
LOGIC AND
PROTECTION
RIG
4
1 23
P
D
S
I
TOPFET
January 1996 1 Rev 1.000