1
Standard ICs
Triple 2-channel analog multiplexer /
demultiplexer
BU4053BC / BU4053BCF / BU4053BCFV
The BU4053BC, BU4053BCF, and BU4053BCFV are multiplexers / demultiplexers capable of selecting and combin-
ing analog signals and digital signals in a 2 ch · 3 configuration. Inhibit signals and control signals are used to turn
on the switch corresponding to each of the channels. In addition, even if the logical amplitude (VDD-VSS) of the control
signal is low, signals with a large amplitude (VDD-VEE) can be switched.
Also, as each switch has a low ON resistance, it can be connected to a low impedance circuit.
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Logic circuit diagram
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Truth table
VDD (16)
INH (6)
B (10)
A (11)
C (9)
VSS (8)
VEE (7)
Z0 (5)
Z1 (3)
(4) Z
Y0 (2)
Y1 (1)
(15) Y
X0 (12)
X1 (13)
(14) X
LEVEL
CONVERTER
BINARY TO 1of 2
DECODER WITH INH
INH A B C ON SWITCH
L LLL
LHLL
LLHL
LHHL
LLLH
LHLH
LLH
L HHH
H X X X NONE
X0 Y0 Z0
X1 Y0 Z0
X0 Y1 Z0
X1 Y1 Z0
X0 Y0 Z1
X1 Y0 Z1
X0 Y1 Z1
X1 Y1 Z1
X: Irrelevant
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Block diagram
Y1 1
Y0 2
Z1 3
Z 4
Z0 5
INH 6
VEE 7
VSS 8
16
15
14
13
12
11
10
9
VDD
Y
X
X1
X0
A
B
C
C
Z
INH
VEE
Y
X
A
B
Y0
Z1
Z0
Y1
X1
X0