1
Standard ICs
Quad D latch
BU4042B
The BU4042B is a four-circuit D latch with a common clock line and separate data input terminals.
When the polarity input is set to “H”, input (D) is presented to output (Q) as is, as long as the clock input is rising, and
when the clock input falls, output (Q) holds input (D) at that point. While the clock input is falling, output (Q) does not
change even if input (D) changes.
Also, if the polarity input is set to “L”, input (D) is presented to output (Q) as is, as long as the clock input is at “L”
level, and when the clock input goes to “H” level, latching takes place.
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Features
1) Low power dissipation.
2) Wide range of operating power supply voltages.
3) High input impedance.
4) High fan-out.
5) Direct drive of 2 L-TTL inputs and 1LS-TTL input.
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Block diagram
Q4 1
Q1 2
Q1 3
D1 4
CLOCK 5
POLARITY 6
D2 7
VSS 8
VDD16
Q415CL D
D414
D313
Q312
Q311
Q210
Q29
QQ
CL D
QQ
CL D
QQ
CL D
QQ
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Logic circuit diagram
(6)
LATCH
1
D1 (4)
D2 (7)
D3 (13)
D4 (14)
CLOCK
(5)
POLARITY
(3)
(10)
(9)
(11)
(12)
(1)
(15)
(2)
Q1
Q2
Q2
Q3
Q3
Q4
Q4
LATCH
2
LATCH
3
LATCH
4
Q1
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Truth table
CLOCK POLARITY Q
LL D
H L LATCH
HH D
L H LATCH