1
Standard ICs
8-bit static shift register
BU4021B / BU4021BF
The BU4021B and BU4021BF are 8-bit static shift registers consisting of 8 register cells, each of which has parallel
input. Control of the parallel / serial control input (P / S) enables serial input / serial output with clock synchronization,
as well as parallel input / serial output conversions.
•
Logic circuit diagram
•
Truth table
Serial operation
D
Ds
(11)
P / S
(9)
CLOCK
(10)
Q
C
DQ
C
DQ
C
DQ
C
DQ
C
DQ
Q
C
DQ
Q
C
D
Q
C
(2)
Q6
P8
(1)
P7
(15)
P6
(14)
P5
(13)
P4
(4)
P3
(5)
P2
(6)
P1
(7)
(12)
Q7
(3)
Q8
t CLOCK
nLL0??
n + 1H 10?
n + 2 LL010
n + 3 HL101
XL
Q6 Q7 Q8
Q6 Q7 Q8
DS P / S
(t = n + 6) (t = n + 7) (t = n + 8)
•
Block diagram
2Q6
P8
P4
P3
P2
P1
Q8 3
4
5
6
7
8
15
14
13
12
11
10
9VSS
1
P7
VDD
P5
Q7
DS
CLOCK
P6
P / S
16
Q6
P8
P4
P3
P2
P1
Q8
P7
P5
Q7
DS
CLOCK
P6
P / S
CLOCK
XHL L
XHH H
DS Dm Qm
*
X: Irrelevant
*
: Q6, Q7, and Q8 are external
P / S
•
Absolute maximum ratings (VSS = 0V, Ta = 25°C)
Parameter Symbol Limits Unit
Power supply voltage VDD V
Power dissipation mW
Operating temperature Topr °C
Storage temperature Tstg °C
Input voltage VIN – 0.3 ~ VDD + 0.3 V
1000 (DIP), 500 (SOP) Pd
– 0.3 ~ + 18
– 40 ~ + 85
– 55 ~ + 150
Parallel operation