May 1995

BSS138
N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description Features
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Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter BSS138 Units
VDSS Drain-Source Voltage 50 V
VDGR Drain-Gate Voltage (RGS < 20KΩ) 50 V
VGSS Gate-Source Voltage - Continuous ± 20 V
- Non Repetitive (TP < 50 µS) ± 40
ID Drain Current - Continuous 0.22 A
- Pulsed 0.88
PD Maximum Power Dissipation 0.36 W
Derate Above 25°C 2.8 mW/°C
TJ,TSTG Operating and Storage Temperature Range -55 to 150 °C
TL Maximum Lead Temperature for Soldering
Purposes, 1/16" from Case for 10 Seconds
300 °C
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction to Ambient 350 °C/W
BSS138 Rev. A1
0.22 A, 50V. RDS(ON) = 3.5Ω @ VGS = 10V.
High density cell design for extremely low RDS(ON).
Rugged and Relaible
Compact industry standard SOT-23 surface mount
package.
D
SG
These N-Channel enhancement mode field effect
transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. These products
have been designed to minimize on-state resistance
while provide rugged, reliable, and fast switching
performance. These products are particularly suited for
low voltage, low current applications such as small
servo motor control, power MOSFET gate drivers, and
other switching applications.
© 1997 Fairchild Semiconductor Corporation