Revision 2.2
April 2001
1
BSI
A6
Ultra Low Power/Voltage CMOS SRAM
32K X 8 bit
POWER DISSIPATION
SPEED
(ns)
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Vcc=
2.0V
Vcc=
3.0V
Vcc=
2.0V
Vcc=
3.0V
Vcc=
2.0V
PKG
TYPE
BS62UV256SC SOP-28
BS62UV256TC TSOP-28
BS62UV256PC PDIP-28
BS62UV256JC SOJ-28
BS62UV256DC
+0
O
C to +70
O
C 1.8V ~ 3.6V 150 0.2uA 0.1uA 20mA 10mA
DICE
BS62UV256SI SOP-28
BS62UV256TI TSOP-28
BS62UV256PI PDIP-28
BS62UV256JI SOJ-28
BS62UV256DI
-40
O
C to +85
O
C 1.8V ~ 3.6V 150 0.4uA 0.3uA 25mA 15mA
DICE
• Ultra low operation voltage : 1.8V ~ 3.6V
• Ultra low power consumption :
Vcc = 2.0V C-grade : 10mA (Max.) operating current
I- grade : 15mA (Max.) operating current
0.005uA (Typ.) CMOS standby current
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.01uA (Typ.) CMOS standby current
• High speed access time :
-15 150ns (Max.) at Vcc = 2.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
The BS62UV256 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 32,768 words by 8 bit
and operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both h
speed and low power features with a typical CMOS standby current
0.005uA and maximum access time of 150ns in 2V operation.
Easy memory expansion is provided by an active LOW
enable (CE), and active LOW output enable (OE) and three-st
output drivers.
The BS62UV256 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62UV256 is available in the JEDEC standard 28
330mil Plastic SOP, 8mmx13.4mm TSOP (normal type), 300mi
SOJ and 600mil Plastic DIP.
s
igh
of
chip
ate
pin
l Plastic
„ DESCRIPTION
„ FEATURES
„ BLOCK DIAGRAM
„ PRODUCT FAMILY
„ PIN CONFIGURATIONS
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Address
Input
Buffer
Row
Decoder
Memory Array
512 x 512
Column I/O
Sense Amp
Write Driver
Column Decoder
Data
Buffer
Output
Address Input Buffer
A3 A2 A1 A0 A10
Data
Buffer
Input
Control
Gnd
Vdd
OE
WE
CE
DQ5
DQ4
A12
A8
A7
8
8
8
8
DQ7
DQ6
DQ3
DQ2
DQ1
DQ0
A11
A9
A5
12
64
512
512
18
A14
A13
A4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
BS62UV256
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C
•
•
R0201-BS62UV256
BS62UV256TC
BS62UV256TI
BS62UV256SC
BS62UV256SI
BS62UV256PC
BS62UV256PI