BSI Ultra Low Power/High Speed CMOS SRAM 256K X 16 bit BS616UV4016
R0201-BS616UV4016 1 Revision 1.3
Sep. 2005
n FEATURES
Wide VCC operation voltage :
C-grade : 1.8V ~ 3.6V
I-grade : 1.9V ~ 3.6V
(VCC_min.=1.65V at 25OC)
Ultra low power consumption :
VCC = 2.0V C-grade : 10mA(Max.) operating current
I-grade : 12mA(Max.) operating current
0.3uA (Typ.) CMOS standby current
VCC = 3.0V C-grade : 13mA(Max.) operating current
I-grade : 15mA(Max.) operating current
0.45uA (Typ.) CMOS standby current
High speed access time :
-85 85ns (Max.)
-10 100ns (Max.)
Automatic power down when chip is deselected
Easy expansion with CE and OE options
I/O Configuration x8/x16 selectable by LB and UB pin.
Three state outputs and TTL compatible
Fully static operation
Data retention supply voltage as low as 1.2V
n DESCRIPTION
The BS616UV4016 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates form a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with typical CMOS standby current of
0.3uA at 2.0V/25OC and maximum access time of 85ns at 85OC.
Easy memory expansion is provided by an active LOW chip enable (CE)
and active LOW output enable (OE) and three-state output drivers.
The BS616UV4016 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV4016 is available in DICE form, JEDEC standard 44-pin
TSOP Type II and 48-ball BGA package.

n PRODUCT FAMILY
POWER DISSIPATION SPEED
(ns) STANDBY (I
CCSB1, Max)
Operating
(ICC, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
VCC
RANGE C-grade : 1.8~3.6V
I-grade : 1.9~3.6V VCC=3.0V VCC=2.0V VCC=3.0V VCC=2.0V
PKG TYPE
BS616UV4016DC DICE
BS616UV4016EC TSOP2-44
BS616UV4016AC
+0OC to +70OC 1.8V ~ 3.6V 85/100 6.0uA 3.0uA 13mA 10mA
BGA-48-0608
BS616UV4016DI DICE
BS616UV4016EI TSOP2-44
BS616UV4016AI
-40OC to +85OC 1.9V ~ 3.6V 85/100 8.0uA 5.0uA 15mA 12mA
BGA-48-0608

n PIN CONFIGURATIONS




















n BLOCK DIAGRAM







Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
G
H
F
E
D
C
B
A
1 2 3 4 5 6
A9 A11 A10 NC
A12
A14
A13
A15
WE
IO13 IO5
IO7
IO6
A17
A16
A7
VSS
VCC
IO12
IO11
IO4
IO3
NC
A5
OE
A3
A0
A6
A4
A1 A2 NC
LB
IO10 IO1
CE
IO2
IO0
48-ball BGA top view
UB
IO8
IO9
VSS
VCC
IO14
IO15
NC
NC
A8
A4
A3
A2
A1
A0
CE
IO0
IO1
IO2
IO3
VCC
GND
IO4
IO5
IO6
IO7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
BS616UV4016EC
BS616UV4016EI
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
IO15
IO14
IO13
IO12
GND
VCC
IO11
IO10
IO9
IO8
NC
A8
A9
A10
A11
A12
Address
Input
Buffer
Row
Decoder
Memory Array

1024 x 4096
Column I/O
Write Driver
Sense Amp
Column Decoder
Address Input Buffer
Data
Input
Buffer
Control
IO0
.
.
.
.
.
.
IO15
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
16
16
16
16
8
256
2048
1024 10
A13
Data
Output
Buffer
CE
WE
OE
UB
LB
VCC
GND
A14
.
.
.
.
.
.
A15A16A17A0 A2 A1