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BS616LV8023

器件描述:Very Low Power/Voltage CMOS SRAM 512K x 16 or 1M x 8 bit switchable
器件厂商:BSI [Brilliance Semiconductor]
文件大小:204.08KB,共11页
Sponsor by e络盟
器件资料摘要:
Revision 2.0
April 2002
1
Very Low Power/Voltage CMOS SRAM
512K x 16 or 1M x 8 bit switchable
BS616LV8023
R0201-BS616LV8023
The BS616LV8023 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits or
1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.5uA and maximum access time of 70/100ns in 3.0V operation.
Easy memory expansion is provided by an active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
The BS616LV8023 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8023 is available in 48-pin BGA type.
POWER DISSIPATION
SPEED
(ns)
STANDBY
(ICCSB1, Max)
Operating
(ICC
PRODUCT
FAMILY
PKG TYPE
BS616LV8023BC +0
O
C to +70
O
C 2.4V ~ 3.6V 70 / 100 3uA 20mA BGA-48-0810
BS616LV8023BI -40
O
C to +85
O
C 2.4V ~ 3.6V 70 / 100 6uA 25mA BGA-48-0810
• Very low operation voltage : 2.4 ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc= 3.0V
-10 100ns (Max.) at Vcc= 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
„ DESCRIPTION„ FEATURES
„ BLOCK DIAGRAM
„ PRODUCT FAMILY
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Row
Decoder
Memory Array
2048 x 4096
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A1 A2 A3
Data
Buffer
Input
Control
Vss
Vdd
OE
WE
CE1
D15
D0
A11
A7
A17
A8
A12
A13
16(8)
16(8)
16(8)
16(8)
16(18)
256(512)
4096
204822
A10
A9
A0
A6
A4A16
A14
Address
Input
Buffer
A5
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
A15
CIO
CE2
(SAE)A18
„ PIN CONFIGURATIONS
LB OE A0 A1 A2 CE2
D8 UB A3 A4
CE1
D0
D9
D10
VSS
D3
VCC
VCC
D12
A15
12 A13
WE
D7
A18 A8 A9
A5 A6 D1 D2
D11 A17 A7
A16 D4 VSS
D14 D13 A14 D5 D6
D15 CIO.A
A10 A11 SAE.
A
B
C
D
E
F
G
H
123456
VSS
48-Ball CSP top View
OPERATING
TEMPERATURE
Vcc
RANGE
, Max)
BSI
Vcc=3.0V Vcc=3V
Vcc=3V