Revision 2.4
April 2002
1
Very Low Power/Voltage CMOS SRAM
128K x 16 or 256K x 8 bit switchable
The BS616LV2025 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits or
262,144 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.6uA and maximum access time of 70/55 ns in 5V operation.
Easy memory expansion is provided by active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
The BS616LV2025 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2025 is available in DICE form and 48-pin BGA type.
POWER DISSIPATION
SPEED
( ns )
STANDBY
( ICCSB1, Max )
Operating
( ICC, Max )
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Vcc=5.0V Vcc=5.0V Vcc=5.0V
PKG TYPE
BS616LV2025DC DICE
BS616LV2025AC
+0
O
C to +70
O
C 4.5V ~ 5.5V 70 / 55 6uA 40mA
BGA-48-0608
BS616LV2025DI DICE
BS616LV2025AI
-40
O
C to +85
O
C 4.5V ~ 5.5V 70 / 55 25uA 45mA
BGA-48-0608
• Very low operation voltage : 4.5 ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 40mA (Max.) operating current
I -grade: 45mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 5.0V
-55 55ns (Max.) at Vcc = 5.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
„ DESCRIPTION„ FEATURES
„ BLOCK DIAGRAM
„ PRODUCT FAMILY
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
BS616LV2025
Row
Decoder
Memory Array
1024 x 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A1 A2 A3
Data
Input
Buffer
Control
Vss
Vdd
OE
WE
D0
A8
A12
16(8)
16(8)
16(8)
16(8)
CE1
D15
A11
A7
A13
14(16)
128(256)
2048
102420
A10
A9
A0
A6
A4A16
A14
Address
Input
Buffer
A5
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
A15
CIO
CE2
(SAE)
„ PIN CONFIGURATION
R0201-BS616LV2025
BSI