EEWorld首页 新闻 论坛 博客 白皮书 专题 电子电路 电子器件 单片机 嵌入式 模拟电路 DSP FPGA 电源管理 手机/便携 医疗电子 汽车电子 工业控制
厂商索引:A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V-W-X-Y-Z

BS616LV2011

器件描述:Very Low Power/Voltage CMOS SRAM 128K X 16 bit
器件厂商:BSI [Brilliance Semiconductor]
文件大小:237.08KB,共11页
Sponsor by e络盟
器件资料摘要:
R0201-BS616LV2011 Revision 2.5
April 2002
1
Very Low Power/Voltage CMOS SRAM
128K X 16 bit
• Very low operation voltage : 2.4 ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade: 25mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 40mA (Max.) operating current
I -grade: 45mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 3.0V
-10 100ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
„ FEATURES
The BS616LV2011 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.1uA and maximum access time of 70/100ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE), active LOW output enable(OE) and three-state output
drivers.
The BS616LV2011 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2011 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package , JEDEC standard 48-pin TSOP Type I package
and 48-ball BGA package.
„ DESCRIPTION
Row
Decoder
Memory Array
1024 x 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A3 A2 A1
Data
Input
Buffer
Control
Gnd
Vcc
OE
DQ0
A16
A7
A15
16
16
16
16
WE
CE
DQ15
A5
A6
A13
14
128
2048
„ BLOCK DIAGRAM
102420
A14
A12
A9
A4
A0A11
A8
Address
Input
Buffer
A10
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
„ PRODUCT FAMILY
„ PIN CONFIGURATIONS
Bril reserves the right to modify document contents without notice.liance Semiconductor Inc.
BS616LV2011
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A16
A15
A14
A13
A12
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
1
2
3
4
14
16
19
21
22
43
31
29
27
25
23
5
6
7
8
9
10
11
12
39
38
37
36
35
34
33
BS616LV2011EC
BS616LV2011EI
13
15
17
18
20
44
42
41
40
32
30
28
26
24
POWER DISSIPATION
SPEED
( ns )
STANDBY
( ICCSB1, Max )
Operating
( ICC, Max )
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Vcc=
3.0V
Vcc=
3.0V
Vcc=
5.0V
Vcc=
3.0V
Vcc=
5.0V
PKG TYPE
BS616LV2011DC DICE
BS616LV2011EC TSOP2-44
BS616LV2011TC TSOP1-48
BS616LV2011AC
+0
O
C to +70
O
C 2.4V ~ 5.5V 70/100
40mA
BGA-48-0608
0.7uA 6uA 20mA
BS616LV2011DI DICE
BS616LV2011EI TSOP2-44
BS616LV2011TI TSOP1-48
BS616LV2011AI
-40
O
C to +85
O
C 2.4V ~ 5.5V 70/100
45mA
BGA-48-0608
1.5uA 25uA 25mA
48-ball BGA top view
G
H
F
E
D
C
A9A8
D15
D14
VSS
D9
D13 A14
D12
D11
D10 A5
B D8 A3
A0
A11A10
A15 D5
A16
A7
A6
D4
D3
D1
D7
D6
D2
A4
A1 A2
D0
N.C.VCC VSS
VCC
N.C.
CE
N.C.N.C.
N.C.
N.C.
A12 A13
WE
ALB
1
UB
OE
23456
BSI