Revision 2.2
April 2001
1
R0201-BS616LV1010
POWER DISSIPATION
SPEED
(ns)
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Vcc=3.0V Vcc=5.0V Vcc=3.0V Vcc=5.0V Vcc=3.0V
PKG TYPE
BS616LV1010EC TSOP2-44
BS616LV1010AC
+0
O
C to +70
O
C 2.4V ~ 5.5V 70 3uA 0.5uA 35mA 20mA
BGA-48-0608
BS616LV1010EI TSOP2-44
BS616LV1010AI
-40
O
C to +85
O
C 2.4V ~ 5.5V 70 5uA 1.5uA 40mA 25mA
BGA-48-0608
Very Low Power/Voltage
64K X 16 bit
CMOS SRAM
• Very low operation voltage : 2.4 ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.02uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns (Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
The BS616LV1010 is a high performance, very low power CMOS Static
Random Access Memory organized as 65,536 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.02uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable(CE) and active LOW output enable(OE) and three-state output
drivers.
The BS616LV1010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV1010 is available in the JEDEC standard 44-pin TSOP
Type II and 48-pin BGA package.
„ DESCRIPTION
„ FEATURES
Row
Decoder
Memory Array
512 x 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
A3 A2 A1
Data
Input
Buffer
Control
Gnd
Vcc
OE
DQ0
16
16
16
16
WE
CE
DQ15
A5
A6
A7
A15
A13
14
128
2048
„ BLOCK DIAGRAM
51218
A14
A12
A9
A4
A0A11
A8
Address
Input
Buffer
A10
Address Input Buffer
.
.
.
.
UB
.
.
.
.
LB
„ PRODUCT FAMILY
„ PIN CONFIGURATIONS
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
BS616LV1010
G
H
F
E
D
C
B
A
12345
A9A8NC
IO15 NC A12
NCA11A10
A13 WE IO7
IO14
VCC
VSS
IO9
IO13 A14
IO12
IO11
IO10
NC
NC
A5
IO8
LB
UB
OE
A3
A0
A15 IO5
NC
A7
A6
IO4
IO3
IO1
IO6
VSS
VCC
IO2
A4
A1
CE
A2
IO0
NC
6
A4
A3
A2
A1
A0
CE
DQ0
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ7
DQ1
DQ6
WE
A15
A14
A13
A12
NC
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
1
2
3
4
5
6
7
9
10
11
12
13
14
16
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
BS616LV1010EC
BS616LV1010EI
8
15
17
18
20
22
28
26
24
23
19
21
29
27
25
BSI