BS108
器件描述：200 VOLTS N-CHANNEL TMOS POWER FET LOGIC LEVEL
器件厂商：MOTOROLA [Motorola, Inc]
文件大小：58.88KB，共4页
Sponsor by e络盟器件资料摘要：
Motorola, Inc. 1997
C0076C0111C0103C0105C0099 C0076C0101C0118C0101C0108 C0084C0077C0079C0083
N–Channel Enhancement Mode
This TMOS FET is designed for high voltage, high speed
switching applications such as line drivers, relay drivers, CMOS
logic, microprocessor or TTL to high voltage interface and high
voltage display drivers.
• Low Drive Requirement, V
GS
= 3.0 V max
• Inherent Current Sharing Capability Permits Easy Paralleling of
many Devices
MAXIMUM RATINGS
Rating Symbol Value Unit
Drain–Source Voltage V
DSS
200 Vdc
Gate–Source Voltage V
GS
±20 Vdc
Drain Current
Continuous
(1)
Pulsed
(2)
I
D
I
DM
250
500
mAdc
Total Power Dissipation
@ T
A
= 25°C
Derate above T
A
= 25°C
P
D
350
6.4
mW
mW/°C
Operating and Storage Temperature Range T
J
, T
stg
–55 to +150 °C
1. The Power Dissipation of the package may result in a lower continuous drain current.
2. Pulse Test: Pulse Width C0118 300 µs, Duty Cycle C0118 2.0%.
TMOS is a registered trademark of Motorola, Inc.
Order this document
by BS108/D
C0077C0079C0084C0079C0082C0079C0076C0065
SEMICONDUCTOR TECHNICAL DATA
C0066C0083C0049C0048C0056
200 VOLTS
N–CHANNEL TMOS
POWER FET
LOGIC LEVEL
CASE 29–04, STYLE 30
TO–92
1
2
3
1 DRAIN
2
GATE
3 SOURCE
C0076C0111C0103C0105C0099 C0076C0101C0118C0101C0108 C0084C0077C0079C0083
N–Channel Enhancement Mode
This TMOS FET is designed for high voltage, high speed
switching applications such as line drivers, relay drivers, CMOS
logic, microprocessor or TTL to high voltage interface and high
voltage display drivers.
• Low Drive Requirement, V
GS
= 3.0 V max
• Inherent Current Sharing Capability Permits Easy Paralleling of
many Devices
MAXIMUM RATINGS
Rating Symbol Value Unit
Drain–Source Voltage V
DSS
200 Vdc
Gate–Source Voltage V
GS
±20 Vdc
Drain Current
Continuous
(1)
Pulsed
(2)
I
D
I
DM
250
500
mAdc
Total Power Dissipation
@ T
A
= 25°C
Derate above T
A
= 25°C
P
D
350
6.4
mW
mW/°C
Operating and Storage Temperature Range T
J
, T
stg
–55 to +150 °C
1. The Power Dissipation of the package may result in a lower continuous drain current.
2. Pulse Test: Pulse Width C0118 300 µs, Duty Cycle C0118 2.0%.
TMOS is a registered trademark of Motorola, Inc.
Order this document
by BS108/D
C0077C0079C0084C0079C0082C0079C0076C0065
SEMICONDUCTOR TECHNICAL DATA
C0066C0083C0049C0048C0056
200 VOLTS
N–CHANNEL TMOS
POWER FET
LOGIC LEVEL
CASE 29–04, STYLE 30
TO–92
1
2
3
1 DRAIN
2
GATE
3 SOURCE