March 2001
AS29LV800
CC
V
SS
Input/outputErase voltage
X decoder Cell matrix
Y decoder Y gating
Data latchChip enable
A
d
dr
es
s
la
t
c
h
buffers
Command
register
Program/erase
control
V
CC
detector
generator
Program voltage
generator
Timer
A0–A18
CE
OE
STB
STB
Output enable
Logic
WE
RESET
BYTE
A-1
Selection guide
29LV800-70
Maximum access time t
AA
70
Maximum chip enable access time t
CE
70
3/22/01; V.1.0 Alliance Semicond
* Regulated voltage range of 3.0 to 3.6V
Maximum output enable access time t
OE
30
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A14
A15
A16
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
A6
A5
A4
A3
A2
A1
A0
CE
V
SS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
21
22
DQ3
DQ11
A10
A11
A12
A13
2A18
3A17
4A7
1RY/BY
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
WE
A8
A9
RESET
A8 A9
0 1 2 3 4 5
A1
6
BY
T
E
V
SS
DQ1
5
/
A
-1
DQ
7
DQ
14
NCNCWE
E
T
NCNC
B
Y8
DQ
2
DQ
10
DQ
3
DQ
11
V
CC
DQ
4
DQ
12
DQ
5
DQ
6
DQ
13
1234567891011121314
4847464544434241403938373635
1516
3433
7
A7A6A5A4A3A2A1
A0 CE V
SS
OE DQ
0
DQ
8
DQ
1
DQ
9
171819202122
323130292827
2324
2625
AS29LV800
A
S
29
L
V
80
0
R
*
29LV800-80 29LV800-90 29LV800-120 Unit
80 90 120 ns
80 90 120 ns
- One 8K; two 4K; one 16K; and fifteen 32K word sectors
- Boot code sector architecture—T (top) or B (bottom)
- Erase any combination of sectors or full chip
Single 2.7-3.6V power supply for read/write operations
Sector protection
High speed 70/80/90/120 ns address access time
Automated on-chip programming algorithm
- Automatically programs/verifies data at specified address
Automated on-chip erase algorithm
- Automatically preprograms/erases chip or specified
sectors
Hardware RESET pin
- Resets internal state machine to read mode
Logic block diagram
V
Sector protect/
RY/BY DQ0–DQ15
switches
erase voltage
JEDEC standard software, packages and pinouts
- 48-pin TSOP
- 44-pin SO; availability TBD
Detection of program/erase cycle completion
- DQ7 DATA polling
- DQ6 toggle bit
- DQ2 toggle bit
-RY/BY output
Erase suspend/resume
- Supports reading data from or programming data to a
sector not being erased
Low V
CC
write lock-out below 1.5V
10 year data retention at 150C
100,000 write/erase cycle endurance
Pin arrangement
44-pin SO
A1 A1 A1 A1 A1 A1
RES
RY
/A1
48-pin TSOP
A1
®
3V 1M × 8/512K × 16 CMOS Flash EEPROM
Features
• Organization: 1M×8/512K×16
Sector architecture
- One 16K; two 8K; one 32K; and fifteen 64K byte sectors
Low power consumption
- 200 nA typical automatic sleep mode current
- 200 nA typical standby current
- 10 mA typical read current
Copyright © Alliance Semiconductor. All rights reserved.
uctor P. 1 of 25
30 35 50 ns