Features
a174 Power monitoring, backup supply,
and switching for 3V battery-
backup applications
a174 Write-protect control
a174 Input decoder for control of up to
2 banks of SRAM
a174 3-volt backup power output
a174 Internal 130mAh lithium-coin
cell
a174 Reset output for system power-on
reset
a174 Less than 10ns chip-enable
propagation delay
a174 5% or 10% supply operation
General Description
The CMOS bq2502 Integrated Backup
Unit provides all the necessary func-
tions for converting one or two
banks of standard CMOS SRAM
into nonvolatile read/write memory.
A precision comparator monitors the 5V
V
CC
input for an out-of-tolerance condi-
tion. When out of tolerance is detected,
the two conditioned chip-enable outputs
are forced inactive to write-protect both
banks of SRAM.
Power for the external SRAMs is
switched from the V
CC
supply to the
internal battery-backup supply as
V
CC
decays. On a subsequent
power-up, the V
OUT
supply is auto-
matically switched from the internal
lithium supply to the V
CC
supply.
The external SRAMs are write-pro-
tected until a power-valid condition
exists. The reset output provides
power-fail and power-on resets for the
system.
During power-valid operation, the
input decoder selects one of two
banks of SRAM.
The internal lithium cell is initially
electrically isolated, protecting the
battery from accidental discharge.
Connection to the battery is made
only after the first application of
V
CC
.
1
Integrated Backup Unit
bq2502
1
PN250201.eps
12-Pin 600-mil DIP Module
2
3
4
5
6
12
11
10
9
8
7
V
CC
CE
CE
CON1
CE
CON2

NC
RST
V
OUT
NC
A
NC
THS
V
SS
Pin Names
VOUT Supply output
RST Reset output
THS Threshold select input
CE chip-enable active low input
CECON1, Conditioned chip-enable outputs
CECON2
A Bank select input
NC No connect
VCC 5-volt supply input
VSS Ground
Two banks of CMOS static RAM can be battery-backed
using the V
OUT
and conditioned chip-enable output pins
from the bq2502. As the voltage input V
CC
slews down
during a power failure, the two conditioned chip-enable
outputs, CE
CON1
and CE
CON2
, are forced inactive
independent of the chip-enable input CE.
This activity unconditionally write-protects external SRAM
as V
CC
falls to an out-of-tolerance threshold V
PFD
.V
PFD
is
selected by the threshold-select input pin, THS. If THS is
tied to V
SS
, the power-fail detection occurs at 4.62V typical
for 5% supply operation.
Apr. 1991
Functional Description
Pin Connections
If THS is tied to V
OUT
, power-fail detection occurs at
4.37V typical for 10% supply operation. The THS pin
must be tied to V
SS
or V
OUT
for proper operation.
If a memory access is in process to any of the two exter-
nal banks of SRAM during power-fail detection, that
memory cycle continues to completion before the memory
is write-protected. If the memory cycle is not terminated
within time t
WPT
(150µs maximum), the two chip-enable
outputs are unconditionally driven high, write-protecting
the controlled SRAMs.