Features
Be4 Power monitoring and switching
for 3-volt battery-backup applica-
tions
Be4 Write-protect control
Be4 2-input decoder for control of up
to 4 banks of SRAM
Be4 3-volt primary cell inputs
Be4 Less than 10ns chip-enable
propagation delay
Be4 5% or 10% supply operation
General Description
The CMOS bq2204A SRAM Non-
volatile Controller Unit provides all
necessary functions for converting
up to four banks of standard CMOS
SRAM into nonvolatile read/write
memory.
A precision comparator monitors the 5V
V
CC
input for an out-of-tolerance condi-
tion. When out-of-tolerance is detected,
the four conditioned chip-enable outputs
are forced inactive to write-protect up to
four banks of SRAM.
During a power failure, the external
SRAMs are switched from the V
CC
supply to one of two 3V backup sup-
plies. On a subsequent power-up, the
SRAMs are write-protected until a
power-valid condition exists.
During power-valid operation, a
two-input decoder transparently se-
lects one of up to four banks of
SRAM.
1
Dec. 1992 B
bq2204A
X4 SRAM Nonvolatile Controller Unit
1
PN220401.eps
16-Pin Narrow DIP or SOIC
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
BC
1
CE
CE
CON1

CE
CON2
CE
CON3
CE
CON4
NC
V
OUT
BC
2
NC
A
B
NC
THS
V
SS
Pin Names
VOUT Supply output
BC1–BC2 3 volt primary backup cell inputs
THS Threshold select input
CE chip-enable active low input
CECON1– Conditioned chip-enable outputs
CECON4
A–B Decoder inputs
NC No connect
VCC +5 volt supply input
VSS Ground
Up to four banks of CMOS static RAM can be battery-
backed using the V
OUT
and conditioned chip-enable out-
put pins from the bq2204A. As V
CC
slews down during
a power failure, the conditioned chip-enable outputs
CE
CON1
through CE
CON4
are forced inactive independ-
ent of the chip-enable input CE.
This activity unconditionally write-protects the external
SRAM as V
CC
falls below an out-of-tolerance threshold
V
PFD
.V
PFD
is selected by the threshold select input pin,
THS. If THS is tied to V
SS
, the power-fail detection occurs
at 4.62V typical for 5% supply operation.
If THS is tied to V
CC
, power-fail detection occurs at
4.37V typical for 10% supply operation. The THS pin
must be tied to V
SS
or V
CC
for proper operation.
If a memory access is in process to any of the four external
banks of SRAM during power-fail detection, that memory
cycle continues to completion before the memory is write-
protected. If the memory cycle is not terminated within
time t
WPT
, all four chip-enable outputs are unconditionally
driven high, write-protecting the controlled SRAMs.
Pin Connections
Functional Description