Features
Be4 Power monitoring and switching
for nonvolatile control of SRAMs
Be4 Write-protect control
Be4 Input decoder allows control of
up to 2 banks of SRAM
Be4 3-volt primary cell input
Be4 3-volt rechargeable battery in-
put/output
Be4 Reset output for system power-on
reset
Be4 Less than 10ns chip enable
propagation delay
Be4 5% or 10% supply operation
General Description
The CMOS bq2202 SRAM Nonvolatile
Controller With Reset provides all the
necessary functions for converting one
or two banks of standard CMOS
SRAM into nonvolatile read/write
memory.
A precision comparator monitors the
5V V
CC
input for an out-of-tolerance
condition. When out-of-tolerance is
detected, the two conditioned
chip-enable outputs are forced inac-
tive to write-protect both banks of
SRAM.
Power for the external SRAMs is
switched from the V
CC
supply to the
battery-backup supply as V
CC
de-
cays. On a subsequent power--up, the
V
OUT
supply is automatically
switched from the backup supply to
the V
CC
supply. The external SRAMs
are write-protected until a power-
valid condition exists. The reset out-
put provides power-fail and power-on
resets for the system.
During power-valid operation, the
input decoder selects one of two
banks of SRAM.
1
Pin Names
VOUT Supply output
RST Reset output
THS Threshold select input
CE Chip enable active low input
CECON1, Conditioned chip enable outputs
CECON2
A Bank select input
BCP 3V backup supply input
BCS 3V rechargeable backup supply input/output
NC No connect
VCC +5 volt supply input
VSS Ground
Two banks of CMOS static RAM can be battery-backed
using the V
OUT
and conditioned chip-enable output pins
from the bq2202. As the voltage input V
CC
slews down
during a power failure, the two conditioned chip enable
outputs, CE
CON1
and CE
CON2
, are forced inactive
independent of the chip enable input CE.
This activity unconditionally write-protects external
SRAM as V
CC
falls to an out-of-tolerance threshold
V
PFD
.V
PFD
is selected by the threshold select input pin,
THS. If THS is tied to V
SS
, the power-fail detection oc-
curs at 4.62V typical for 5% supply operation.
If THS is tied to V
CC
, power-fail detection occurs at
4.37V typical for 10% supply operation. The THS pin
must be tied to V
SS
or V
CC
for proper operation.
If a memory access is in process to any of the two exter-
nal banks of SRAM during power-fail detection, that
memory cycle continues to completion before the memory
is write-protected. If the memory cycle is not terminated
within time t
WPT
(150µsec maximum), the two chip en-
able outputs are unconditionally driven high, write-
protecting the controlled SRAMs.
SRAM NV Controller With Reset
bq2202
Sept. 1997 D
1
PN220201.eps
16-Pin Narrow DIP or SOIC
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
BC
S
CE
CE
CON1

CE
CON2
NC
RST
NC
V
OUT
BC
P
NC
A
NC
NC
THS
V
SS
Functional Description
Pin Connections