1
FEATURES
‰ 25ns maximum (3.3 volt supply) address access time
‰ Dual cavity package contains two (2) 512K x 8 industry-
standard asynchronous SRAMs; the control architecture
allows operation as an 8-bit data width
‰ TTL compatible inputs and output levels, three-state
bidirectional data bus
‰ Typical radiation performance
- Total dose: 50krad(Si)
- SEL Immune >80 MeV-cm
2
/mg
- LET
TH
(0.25) = >10 MeV-cm
2
/mg
- Saturated Cross Section cm
2
per bit, 5.0E-9
- <1E-8 errors/bit-day, Adams 90% geosynchronous
heavy ion
‰ Packaging options:
- 44-lead bottom brazed dual CFP (BBTFP) (4.6 grams)
‰ Standard Microcircuit Drawing 5962-01532
- QML T and Q compliant part
INTRODUCTION
The QCOTS
TM
UT8Q1024K8 Quantified Commercial Off-the-
Shelf product is a high-performance 1M byte (8Mbit) CMOS
static RAM built with two individual 524,288 x 8 bit SRAMs
with a common output enable. Memory access and control is
provided by an active LOW chip enable (En), an active LOW
output enable (G). This device has a power-down feature that
reduces power consumption by more than 90% when deselected.
Writing to each memory is accomplished by taking one of the
chip enable (En) inputs LOW and write enable (Wn) inputs
LOW. Data on the I/O pins is then written into the location
specified on the address pins (A
0
through A
18
). Reading from
the device is accomplished by taking one of the chip enable (En)
and output enable (G) LOW while forcing write enable (Wn)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
Only one SRAM can be read or written at a time.
The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).
Figure 1. UT8Q1024K8 SRAM Block Diagram
512K x 8 512K x 8
DQ(7:0)
G
A(18:0)
E
1
E
0
W
1
W
0
Standard Products
QCOTS
TM
UT8Q1024K8 SRAM
Data Sheet
January, 2003