TL/F/6427
54LS365A/DM54LS365A/DM74LS365A
Hex
TRI-STATE
Buffers
June 1989
54LS365A/DM54LS365A/DM74LS365A
Hex TRI-STATE Buffers
General Description
This device contains six independent gates each of which
performs a non-inverting buffer function. The outputs have
the TRI-STATE feature. When enabled, the outputs exhibit
the low impedance characteristics of a standard LS output
with additional drive capability to permit the driving of bus
lines without external resistors. When disabled, both the
output transistors are turned off presenting a high-imped-
ance state to the bus line. Thus the output will act neither as
a significant load nor as a driver. To minimize the possibility
that two outputs will attempt to take a common bus to oppo-
site logic levels, the disable time is shorter than the enable
time of the outputs.
Features
Y
Alternate Military/Aerospace device (54LS365A) is
available. Contact a National Semiconductor Sales Of-
fice/Distributor for specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6427–1
Order Number 54LS365ADMQB, 54LS365AFMQB, 54LS365ALMQB,
DM54LS365AJ, DM54LS365AW, DM74LS265AM or DM74LS365AN
See NS Package Number E20A, J16A, M16A, N16E or W16A
Function Table
Y e A
Input Output
G1G2A Y
H X X Hi-Z
X H X Hi-Z
LLH H
L L
HeHigh Logic Level
L e Low Logic Level
X e Either Low or High Logic Level
Hi-Z e TRI-STATE (Outputs are disabled)
TRI-STATE is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.