CONNECTION DIAGRAMS DIP (TOP VIEW)
18 17 16 15 14 13
1234 567
20 19
8
V
CC
DIR
B1 B2 B3 B5B4 B6
A1 A2 A3 A4 A5 A6 A7
910
A8 GND
12 11
B7 B8
18 17 16 15 14 13
1234567
20 19
8
V
CC
DIR
B1 B2 B3 B5B4 B6
A1 A2 A3 A4 A5 A6 A7
910
A8 GND
12 11
B7 B8
SN54/74LS640
SN54/74LS642
SN54/74LS641
SN54/74LS645
ENABLE
G
ENABLE
G
5-1
FAST AND LS TTL DATA
OCTAL BUS TRANSCEIVERS
These octal bus transceivers are designed for asynchronous two-way
communication between data buses. Control function implementation
minimizes external timing requirements. These circuits allow data transmis-
sion from the A bus to B or from the B bus to A bus depending upon the logic
level of the direction control (DIR) input. Enable input (G) can disable the
device so that the buses are effectively isolated.
DEVICE OUTPUT LOGIC
LS640 3-State Inverting
LS641 Open-Collector True
LS642 Open-Collector Inverting
LS645 3-State True
FUNCTION TABLE
CONTROL
INPUTS
OPERATION
LS640 LS641
G DIR LS642 LS645
L L B data to A bus B data to A bus
L H A data to B bus A data to B bus
H X Isolation Isolation
H = HIGH Level, L = LOW Level, X = Irrelevant
SN54/74LS640
SN54/74LS641
SN54/74LS642
SN54/74LS645
OCTAL BUS TRANSCEIVERS
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
20
1
J SUFFIX
CERAMIC
CASE 732-03
20
1
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03