TL/F/10207
54LS168
Synchronous
Bi-Directional
BCD
Decade
Counter
June 1989
54LS168 Synchronous Bi-Directional
BCD Decade Counter
General Description
The 54LS168 is a fully synchronous 4-state up/down coun-
ter featuring a preset capability for programmable operation,
carry lookahead for easy cascading and a U/D input to con-
trol the direction of counting. It counts in the BCD (8421)
sequence and all state changes, whether in counting or par-
allel loading, are initiated by the LOW-to-HIGH transition of
the clock.
Connection Diagram
Dual-In-Line Package
TL/F/10207–1
Order Number 54LS168DMQB,
54LS168FMQB or 54LS168LMQB
See NS Package Number
E20A, J16A or W16A
Logic Symbol
TL/F/10207–2
V
CC
e Pin 16
GND e Pin 8
Pin Names Description
CEP Count Enable Parallel Input (Active LOW)
CET Count Enable Trickle Input (Active LOW)
CP Clock Pulse Input (Active Rising Edge)
P0–P3 Parallel Data Inputs
PE Parallel Enable Input (Active LOW)
U/D Up-Down Count Control Input
Q0–Q3 Flip-Flop Outputs
TC Terminal Count Output (Active LOW)
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.