26CV12
器件描述：High Performance E2CMOS PLD Generic Array Logic
器件厂商：LATTICE [Lattice Semiconductor]
文件大小：255.04KB，共17页
Sponsor by e络盟器件资料摘要：
GAL26CV12
High Performance E
2
CMOS PLD
Generic Array Logic™
1
Features
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 142.8 MHz
— 4.5ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS
®
Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• LOW POWER CMOS
— 90 mA Typical Icc
•E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TWELVE OUTPUT LOGIC MACROCELLS
— Uses Standard 22V10 Macrocells
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
I
I
I
I
I
I
I
I
I
I
I
I
PROGRAMMABLE
AND-ARRAY
(122X52)
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
10
OLMC
I/O/Q
12
OLMC
I/O/Q
12
OLMC
I/O/Q
10
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
I/CLK INPUT
RESET
PRESET
I/O/Q
128
14 15
GND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/O/Q
Vcc
I/CLK
I
I/O/Q
I/O/Q
I/O/Q
I
I
I
I
I/O/Q
I
I
I
I
I
I
I
7
21
I
I
I
VCC
I
I
I
2
I I I
I/O/Q I/O/Q I/O/Q
I/O/Q
I I I I/CLK I I/O/Q I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
I/O/Q
28426
5
7
9
11
12 14 16 18
19
21
23
25
GAL26CV12
Top View
GAL
26CV12
PLCC
DIP
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. June 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
26cv12_03
Description
The GAL26CV12, at 7.5 ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E
2
) floating gate technology to provide the highest
performance 28-pin PLD available on the market. E
2
technology
offers high speed (<100ms) erase times, providing the ability to
reprogram or reconfigure the device quickly and efficiently.
Expanding upon the industry standard 22V10 architecture, the
GAL26CV12 eliminates the learning curve typically associated with
using a new device architecture. The generic architecture provides
maximum design flexibility by allowing the Output Logic Macrocell
(OLMC) to be configured by the user. The GAL26CV12 OLMC is
fully compatible with the OLMC in standard bipolar and CMOS
22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers100% field programmability and functionality
of all GAL products. In addition, 100 erase/write cycles and data
retention in excess of 20 years are specified.
Functional Block Diagram
Pin Configuration
High Performance E
2
CMOS PLD
Generic Array Logic™
1
Features
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 7.5 ns Maximum Propagation Delay
— Fmax = 142.8 MHz
— 4.5ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS
®
Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
• LOW POWER CMOS
— 90 mA Typical Icc
•E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TWELVE OUTPUT LOGIC MACROCELLS
— Uses Standard 22V10 Macrocells
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
I
I
I
I
I
I
I
I
I
I
I
I
PROGRAMMABLE
AND-ARRAY
(122X52)
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
10
OLMC
I/O/Q
12
OLMC
I/O/Q
12
OLMC
I/O/Q
10
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
8
OLMC
I/O/Q
I/CLK INPUT
RESET
PRESET
I/O/Q
128
14 15
GND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/O/Q
Vcc
I/CLK
I
I/O/Q
I/O/Q
I/O/Q
I
I
I
I
I/O/Q
I
I
I
I
I
I
I
7
21
I
I
I
VCC
I
I
I
2
I I I
I/O/Q I/O/Q I/O/Q
I/O/Q
I I I I/CLK I I/O/Q I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
I/O/Q
28426
5
7
9
11
12 14 16 18
19
21
23
25
GAL26CV12
Top View
GAL
26CV12
PLCC
DIP
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. June 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
26cv12_03
Description
The GAL26CV12, at 7.5 ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E
2
) floating gate technology to provide the highest
performance 28-pin PLD available on the market. E
2
technology
offers high speed (<100ms) erase times, providing the ability to
reprogram or reconfigure the device quickly and efficiently.
Expanding upon the industry standard 22V10 architecture, the
GAL26CV12 eliminates the learning curve typically associated with
using a new device architecture. The generic architecture provides
maximum design flexibility by allowing the Output Logic Macrocell
(OLMC) to be configured by the user. The GAL26CV12 OLMC is
fully compatible with the OLMC in standard bipolar and CMOS
22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers100% field programmability and functionality
of all GAL products. In addition, 100 erase/write cycles and data
retention in excess of 20 years are specified.
Functional Block Diagram
Pin Configuration