TL/F/9511
54F/74F273
Octal
D
Flip-Flop
May 1995
54F/74F273
Octal D Flip-Flop
General Description
The ’F273 has eight edge-triggered D-type flip-flops with in-
dividual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock tran-
sition, is transferred to the corresponding flip-flop’s Q out-
put.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements.
Features
Y
Ideal buffer for MOS microprocessor or memory
Y
Eight edge-triggered D flip-flops
Y
Buffered common clock
Y
Buffered, asynchronous Master Reset
Y
See ’F377 for clock enable version
Y
See ’F373 for transparent latch version
Y
See ’F374 for TRI-STATE version
Y
Guaranteed 4000V minimum ESD protection
Commercial Military
Package
Package Description
Number
74F273PC N20A 20-Lead (0.300 Wide) Molded Dual-In-Line
54F273DM (Note 2) J20A 20-Lead Ceramic Dual-In-Line
74F273SC (Note 1) M20B 20-Lead (0.300 Wide) Molded Small Outline, JEDEC
74F273SJ (Note 1) M20D 20-Lead (0.300 Wide) Molded Small Outline, EIAJ
54F273FM (Note 2) W20A 20-Lead Cerpack
54F273LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13 reel. Use suffix e SCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB.
Logic Symbols
TL/F/9511–3
IEEE/IEC
TL/F/9511–5
TRI-STATE is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.