TL/F/9496
54F/74F192
Up/Down
Decade
Counter
with
Separate
Up/Down
Clocks
November 1994
54F/74F192
Up/Down Decade Counter
with Separate Up/Down Clocks
General Description
The ’F192 is an up/down BCD decade (8421) counter. Sep-
arate Count Up and Count Down Clocks are used, and in
either counting mode the circuits operate synchronously.
The outputs change state synchronously with the LOW-to-
HIGH transitions on the clock inputs.
Separate Terminal Count Up and Terminal Count Down out-
puts are used as the clocks for a subsequent stage without
extra logic, thus simplifying multistage counter designs. Indi-
vidual preset inputs allow the circuit to be used as a pro-
grammable counter. Both the Parallel Load (PL) and the
Master Reset (MR) inputs asynchronously override the
clocks.
Features
Y
Guaranteed 4000V minimum ESD protection
Commercial Military
Package
Package Description
Number
74F192PC N16E 16-Lead (0.300 Wide) Molded Dual-In-Line
54F192DM (Note 2) J16A 16-Lead Ceramic Dual-In-Line
74F192SC (Note 1) M16A 16-Lead (0.150 Wide) Molded Small Outline, JEDEC
74F192SJ (Note 1) M16D 16-Lead (0.300 Wide) Molded Small Outline, EIAJ
54F192FM (Note 2) W16A 16-Lead Cerpack
54F192LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13 reel. Use suffix e SCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB.
Logic Symbols Connection Diagrams
TL/F/9496–3
IEEE/IEC
TL/F/9496–6
Pin Assignment for
DIP, SOIC and Flatpak
TL/F/9496–1
Pin Assignment
for LCC
TL/F/9496–2
TRI-STATE is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.