1
Features
• Industry Standard Architecture
– Emulates Many 24-Pin PALs
®
– Low Cost Easy-to-Use Software Tools
• High-Speed Electrically Erasable Programmable Logic Devices
– 7.5 ns Maximum Pin-to-Pin Delay
• Several Power Saving Options
• CMOS and TTL Compatible Inputs and Outputs
• Input and I/O Pull-Up Resistors
• Advanced Flash Technology
– Reprogrammable
– 100% Tested
• High Reliability CMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
• Commercial and Industrial Temperature Ranges
• Dual-in-Line and Surface Mount Packages in Standard Pinouts
Block Diagram
Device I
CC
, Stand-By I
CC
, Active
ATF20V8B 50 mA 55 mA
ATF20V8BQ 35 mA 40 mA
ATF20V8BQL 5 mA 20 mA
High-
Performance
EE PLD
ATF20V8B
Rev. 0407E–05/98
Pin Configurations
Pin Name Function
CLK Clock
I Logic Inputs
I/O Bidirectional Buffers
OE Output Enable
* No Internal Connection
V
CC
+5V Supply
TSSOP Top View
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
VCC
IN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
OE/IN
DIP/SOIC PLCC Top View