ATF16V8CZ
High
Performance
E
2
PLD
ATF16V8CZ
Pin Configurations
Pin Name Function
CLK Clock
I Logic Inputs
I/O Bidirectional Buffers
OE Output Enable
VCC +5V Supply
Features
•
Industry Standard Architecture
Emulates Many 20-Pin PALs

Low Cost Easy-to-Use Software Tools
•
High Speed Electrically Erasable Programmable Logic Devices
12 ns Maximum Pin-to-Pin Delay
•
Low Power - 25 µA Standby Power
•
CMOS and TTL Compatible Inputs and Outputs
Input and I/O Pin Keeper Circuits
•
Advanced Flash Technology
Reprogrammable
100% Tested
•
High Reliability CMOS Process
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200 mA Latchup Immunity
•
Commercial and Industrial Temperature Ranges
•
Dual Inline and Surface Mount Packages in Standard Pinouts
Block Diagram
GND
I/O I/OI8
VccI/CLK
I/OI2 I1
1
11
166
GND
15
16
17
18
19
20
14
13
10
9
8
7
6
5
4
3
2
1 Vcc
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
I/CLK
I1
I2
I3
I4
I5
I6
I7
I8
I/O
I/O
I/O
I/O
I/O
I3
I4
I5
I6
I7
I9/OE
12
11
DIP/SOIC PLCC
Top view
Rev. 0453C/V16FZ-C–04/98
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
I/CLK
I1
I2
I3
I4
I5
I6
I7
I8
GND
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
TSSOP Top View