Top view
ATF16V8C
High
Performance
E
2
PLD
ATF16V8C
Pin Configurations
Pin Name Function
CLK Clock
I Logic Inputs
I/O Bidirectional Buffers
OE Output Enable
VCC +5V Supply
PD Power Down
Features
•
Industry Standard Architecture
Emulates Many 20-Pin PALs

Low Cost Easy-to-Use Software Tools
•
High Speed Electrically Erasable Programmable Logic Devices
5 ns Maximum Pin-to-Pin Delay
•
Low Power - 100 µA Pin-Controlled Power Down Mode Option
•
CMOS and TTL Compatible Inputs and Outputs
I/O Pin Keeper Circuits
•
Advanced Flash Technology
Reprogrammable
100% Tested
•
High Reliability CMOS Process
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200 mA Latchup Immunity
•
Commercial and Industrial Temperature Ranges
•
Dual-in-Line and Surface Mount Packages in Standard Pinouts
Block Diagram
Note: 1. Includes optional PD control pin.
DIP/SOIC PLCC
Rev. 0425D/V16FC-D–04/98
TSSOP Top View
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
I/CLK
I1
I2
PD/I3
I4
I5
I6
I7
I8
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE