SL74LV373


System Logic
Semiconductor
SLS
OCTAL D-TYPE TRANSPARENT LATCH
(3-State)

SL74LV373 are compatible by pinning with SL74HC373 and
SL74HCT373 series. Input voltage levels are compatible with
standard CMOS levels.
• Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
• Voltage supply range: 2.0 to 3.2 V
• LOW input current: 1.0 µÀ; 0.1 µÀ at Ò = 25 °Ñ
• Input current LOW/HIGH: 8 mÀ
• Latch current: not less than 150 mÀ at Ò = 125 °Ñ
• ESD acceptable value: not less than 2000 V as per HBM and
not less than 200 V as per MM
•


ORDERING INFORMATION
SL74LV373N Plastic DIP
SL74LV373D SOIC
TA = -40° to 125° C
for all packages
PIN ASSIGNMENT
373
OE 01
Q0 02
D0 03
D1 04
Q1 05
Q2 06
D2 07
D3 08
Q3 09
GND 10
20
19
18
17
16
15
14
13
12
11
D7
D6
Q6
Q5
D5
D4
Q4
LE
VCC
Q7

FUNCTION TABLE
Inputs Output
OE LE Dn Qn
L H H H
L H L L
L L X no change
H X X Z

BLOCK DIAGRAM

OE 01
Q002D0 03
D1 04 Q105
Q206D2 07
D3 08 Q309
1918
17 16
1514
13 12
11
D7
D6 Q6
Q5D5
D4 Q4
LE
Q7

Pin 20=VCC
Pin 10 = GND