BCR10PN
Nov-29-20011
NPN/PNP Silicon Digital Transistor Array

G01 Switching circuit, inverter, interface circuit,
driver circuit
G01 Two (galvanic) internal isolated NPN/PNP
Transistors in one package
G01 Built in bias resistor (R
1
=10kG02, R
2
=10kG02)
Tape loading orientation
VPS05604
6
3
1
5
4
2
EHA07193
123
456
W1s
Direction of Unreeling
Top View
Marking on SOT-363 package
(for example W1s)
corresponds to pin 1 of device
Position in tape: pin 1
opposite of feed hole side
EHA07176
6 54
321
C1 B2 E2
C2B1E1
1
R
R
2
R
1
R
2
TR1
TR2
Type Marking Pin Configuration Package
BCR10PN W1s 1=E1 2=B1 3=C2 4=E2 5=B2 6=C1
SOT363
Maximum Ratings
Parameter Symbol Value Unit
Collector-emitter voltage V
CEO
50 V
Collector-base voltage V
CBO
50
Emitter-base voltage V
EBO
10
Input on Voltage V
i(on)
20
DC collector current I
C
100 mA
Total power dissipation, T
S
= 115 °C
P
tot
250 mW
Junction temperature T
j
150 °C
Storage temperature T
stg
-65 ... 150
Thermal Resistance
Junction - soldering point
1)
R
thJS
G01 140 K/W
1
For calculation of R
thJA
please refer to Application Note Thermal Resistance