1
Features
• EE Programmable 65,536 x 1, 131,072 x 1 and 262,144 x 1 bit Serial Memories Designed
to Store Configuration Programs for Programmable Gate Arrays
• Simple Interface to SRAM FPGAs Requires Only One User I/O Pin
• Able to Configure with EPF6000 and EPF8000, Flex 10K FPGAs
• Cascadable To Support Additional Configurations or Future Higher-Density Arrays
(17C128/256 only)
• Low-Power CMOS EEPROM Process
• Programmable Reset Polarity
• Available in Industry-Standard Pin-Compatible PLCC Package
• In-System Programmable via 2-Wire Bus
• Emulation of 24CXX Serial EEPROMs
• Available in 3.3V and 5V Versions
Description
The AT17C65/128/256A and AT17LV65/128/256A (AT17A Series) FPGA Configura-
tion EEPROMS (Configurator) provide an easy-to-use, cost-effective configuration
memory for Field Programmable Gate Arrays. The AT17A Series is packaged in the
popular 20-pin PLCC. The AT17A Series family uses a simple serial-access provides
to configure one or more FPGA devices. The AT17A Series organization supplies
enough memory to configure one or multiple smaller FPGAs. Using a special feature
of the AT17A Series, the user can select the polarity of the reset function by program-
ming a special EEPROM bit.
The AT17A Series is pin compatible with the industry standard configurator, and can
be programmed with industry standard programmers.
Pin Configurations
20-Pin PLCC
4
5
6
7
8
18
17
16
15
14
CLK (DCLK)
NC
NC
NC
RESET/OE (RESET/OE)
SER_EN
NC
NC
NC
NC
3 2 1
20 19
9 10 11 12 13
CE (nCS)
GND
NC
CEO (nCASC)
NC
NC DATA NC VCC NC
Rev. 0996A–07/98
FPGA
Configuration
EEPROM
65K, 128K and 256K
AT17CxxxA
AT17LVxxxA