AT1228
器件资料摘要：
PHASE CONTROL THYRISTOR AT1228
Repetitive voltage up to 3200 V
Mean on-state current 1275 A
Surge current 20 kA
FINAL SPECIFICATION
feb 97 - ISSUE : 06
Symbol Characteristic Conditions Tj [°C] Value Unit
BLOCKING
V RRM Repetitive peak reverse voltage 125 3200 V
V RSM Non-repetitive peak reverse voltage 125 3300 V
V DRM Repetitive peak off-state voltage 125 3200 V
I RRM Repetitive peak reverse current V=VRRM 125 100 mA
I DRM Repetitive peak off-state current V=VDRM 125 100 mA
CONDUCTING
I T (AV) Mean on-state current 180° sin, 50 Hz, Th=55°C, double side cooled 1275 A
I T (AV) Mean on-state current 180° sin, 50 Hz, Tc=85°C, double side cooled 1100 A
I TSM Surge on-state current sine wave, 10 ms 125 20 kA
I² t I² t without reverse voltage 2000 x1E3 A²s
V T On-state voltage On-state current = 2900 A 25 2.5 V
V T(TO) Threshold voltage 125 1.2 V
r T On-state slope resistance 125 0.450 mohm
SWITCHING
di/dt Critical rate of rise of on-state current, min. From 75% VDRM up to 1300A, gate 10V 5ohm 125 200 A/µs
dv/dt Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM 125 1000 V/µs
td Gate controlled delay time, typical VD=100V, gate source 25V, 10 ohm , tr=.5 µs 25 1 µs
tq Circuit commutated turn-off time, typical dV/dt = 20 V/µs linear up to 75% VDRM 200 µs
Q rr Reverse recovery charge di/dt=-20 A/µs, I= 870 A 125 µC
I rr Peak reverse recovery current VR= 50 V A
I H Holding current, typical VD=5V, gate open circuit 25 300 mA
I L Latching current, typical VD=5V, tp=30µs 25 700 mA
GATE
V GT Gate trigger voltage VD=5V 25 3.5 V
I GT Gate trigger current VD=5V 25 300 mA
V GD Non-trigger gate voltage, min. VD=VDRM 125 0.25 V
V FGM Peak gate voltage (forward) 30 V
I FGM Peak gate current 10 A
V RGM Peak gate voltage (reverse) 5 V
P GM Peak gate power dissipation Pulse width 100 µs 150 W
P G Average gate power dissipation 2 W
MOUNTING
R th(j-h) Thermal impedance, DC Junction to heatsink, double side cooled 21 °C/kW
R th(c-h) Thermal impedance Case to heatsink, double side cooled 6 °C/kW
T j Operating junction temperature -30 / 125 °C
F Mounting force 22.0 / 24.5 kN
Mass 520 g
ORDERING INFORMATION : AT1228 S 32
standard specification VDRM&VRRM/100
Via N. Lorenzi 8 - I 16152 GENOVA - ITALY
Tel. int. +39/(0)10 6556549 - (0)10 6556488
Fax Int. +39/(0)10 6442510
Tx 270318 ANSUSE I -
ANSALDO Ansaldo Trasporti s.p.a.Unita' Semiconduttori
Repetitive voltage up to 3200 V
Mean on-state current 1275 A
Surge current 20 kA
FINAL SPECIFICATION
feb 97 - ISSUE : 06
Symbol Characteristic Conditions Tj [°C] Value Unit
BLOCKING
V RRM Repetitive peak reverse voltage 125 3200 V
V RSM Non-repetitive peak reverse voltage 125 3300 V
V DRM Repetitive peak off-state voltage 125 3200 V
I RRM Repetitive peak reverse current V=VRRM 125 100 mA
I DRM Repetitive peak off-state current V=VDRM 125 100 mA
CONDUCTING
I T (AV) Mean on-state current 180° sin, 50 Hz, Th=55°C, double side cooled 1275 A
I T (AV) Mean on-state current 180° sin, 50 Hz, Tc=85°C, double side cooled 1100 A
I TSM Surge on-state current sine wave, 10 ms 125 20 kA
I² t I² t without reverse voltage 2000 x1E3 A²s
V T On-state voltage On-state current = 2900 A 25 2.5 V
V T(TO) Threshold voltage 125 1.2 V
r T On-state slope resistance 125 0.450 mohm
SWITCHING
di/dt Critical rate of rise of on-state current, min. From 75% VDRM up to 1300A, gate 10V 5ohm 125 200 A/µs
dv/dt Critical rate of rise of off-state voltage, min. Linear ramp up to 70% of VDRM 125 1000 V/µs
td Gate controlled delay time, typical VD=100V, gate source 25V, 10 ohm , tr=.5 µs 25 1 µs
tq Circuit commutated turn-off time, typical dV/dt = 20 V/µs linear up to 75% VDRM 200 µs
Q rr Reverse recovery charge di/dt=-20 A/µs, I= 870 A 125 µC
I rr Peak reverse recovery current VR= 50 V A
I H Holding current, typical VD=5V, gate open circuit 25 300 mA
I L Latching current, typical VD=5V, tp=30µs 25 700 mA
GATE
V GT Gate trigger voltage VD=5V 25 3.5 V
I GT Gate trigger current VD=5V 25 300 mA
V GD Non-trigger gate voltage, min. VD=VDRM 125 0.25 V
V FGM Peak gate voltage (forward) 30 V
I FGM Peak gate current 10 A
V RGM Peak gate voltage (reverse) 5 V
P GM Peak gate power dissipation Pulse width 100 µs 150 W
P G Average gate power dissipation 2 W
MOUNTING
R th(j-h) Thermal impedance, DC Junction to heatsink, double side cooled 21 °C/kW
R th(c-h) Thermal impedance Case to heatsink, double side cooled 6 °C/kW
T j Operating junction temperature -30 / 125 °C
F Mounting force 22.0 / 24.5 kN
Mass 520 g
ORDERING INFORMATION : AT1228 S 32
standard specification VDRM&VRRM/100
Via N. Lorenzi 8 - I 16152 GENOVA - ITALY
Tel. int. +39/(0)10 6556549 - (0)10 6556488
Fax Int. +39/(0)10 6442510
Tx 270318 ANSUSE I -
ANSALDO Ansaldo Trasporti s.p.a.Unita' Semiconduttori