ASM5I9773A-52-ER
器件描述：2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
器件厂商：ALSC [Alliance Semiconductor Corporation]
厂商主页：http://www.alsc.com/
文件大小：624.66KB，共16页
Sponsor by e络盟器件资料摘要：
June 2005 ASM5I9773A
rev 0.3
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Features
Output frequency range: 8.33MHz to 200MHz
Input frequency range: 6.25MHz to 125MHz
2.5V or 3.3V operation
Split 2.5V / 3.3V outputs
±2%( max ) Output duty cycle variation
12 Clock outputs: drive up to 24 clock lines
One feedback output
Three reference clock inputs: LVPECL or LVCMOS
300pS ( max ) output-output skew
Phase-locked loop (PLL) bypass mode
‘SpreadTrak’
Output enable/disable
Pin-compatible with CY29773, MPC9773 and
MPC973
Industrial temperature range: –40°C to +85°C
52pin 1.0mm TQFP package
RoHS Compliance
Functional Description
The ASM5I9773A is a low-voltage high-performance
200-MHz PLL-based zero delay buffer designed for high
speed clock distribution applications.
The ASM5I9773A features one LVPECL and two LVCMOS
reference clock inputs and provides 12 outputs partitioned
in three banks of four outputs each. Each bank divides the
VCO output per SEL(A:C) settings (see Table 2. Function
Table (Configuration Controls)). These dividers allow
output-to-input ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1,
5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each LVCMOS-compatible
output can drive 50Ω series- or parallel-terminated
transmission lines. For series-terminated transmission
lines, each output can drive one or two traces, giving the
device an effective fanout of 1:24.
The PLL is ensured stable, given that the VCO is
configured to run between 200 MHz to 500 MHz. This
allows a wide range of output frequencies, from 8 MHz to
200 MHz. For normal operation, the external feedback
input FB_IN is connected to the feedback output FB_OUT.
The internal VCO is running at multiples of the input
reference clock set by the feedback divider (see Table 1.
Frequency Table).
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.
rev 0.3
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Features
Output frequency range: 8.33MHz to 200MHz
Input frequency range: 6.25MHz to 125MHz
2.5V or 3.3V operation
Split 2.5V / 3.3V outputs
±2%( max ) Output duty cycle variation
12 Clock outputs: drive up to 24 clock lines
One feedback output
Three reference clock inputs: LVPECL or LVCMOS
300pS ( max ) output-output skew
Phase-locked loop (PLL) bypass mode
‘SpreadTrak’
Output enable/disable
Pin-compatible with CY29773, MPC9773 and
MPC973
Industrial temperature range: –40°C to +85°C
52pin 1.0mm TQFP package
RoHS Compliance
Functional Description
The ASM5I9773A is a low-voltage high-performance
200-MHz PLL-based zero delay buffer designed for high
speed clock distribution applications.
The ASM5I9773A features one LVPECL and two LVCMOS
reference clock inputs and provides 12 outputs partitioned
in three banks of four outputs each. Each bank divides the
VCO output per SEL(A:C) settings (see Table 2. Function
Table (Configuration Controls)). These dividers allow
output-to-input ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1,
5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each LVCMOS-compatible
output can drive 50Ω series- or parallel-terminated
transmission lines. For series-terminated transmission
lines, each output can drive one or two traces, giving the
device an effective fanout of 1:24.
The PLL is ensured stable, given that the VCO is
configured to run between 200 MHz to 500 MHz. This
allows a wide range of output frequencies, from 8 MHz to
200 MHz. For normal operation, the external feedback
input FB_IN is connected to the feedback output FB_OUT.
The internal VCO is running at multiples of the input
reference clock set by the feedback divider (see Table 1.
Frequency Table).
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.