June 2005 ASM2I99456

rev 0.2


Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
3.3V/2.5V LVCMOS Clock Fanout Buffer

Features
ƒ Configurable 10 outputs LVCMOS Clock
distribution buffer
ƒ Compatible to single, dual and mixed 3.3V/2.5V
Voltage supply
ƒ Wide range output clock frequency up to
250MHz
ƒ Designed for mid-range to high-performance
telecom, networking and computer applications
ƒ Supports high-performance differential clocking
applications
ƒ Max. output skew of 200pS
(150pS within one bank)
ƒ Selectable output configurations per output bank
ƒ Tristatable outputs
ƒ 32 LQFP and TQFP Packages
ƒ Ambient Operating temperature range of
-40 to 85°C
ƒ Pin and Function compatible to MPC9456
Functional Description
The ASM2I99456 is a 2.5V and 3.3V compatible 1:10 clock
distribution buffer designed for low-Voltage mid-range to
high-performance telecom, networking and computing
applications. Both 3.3V, 2.5V and dual supply voltages are
supported for mixed-voltage applications. The ASM2I99456
offers 10 low-skew outputs and a differential LVPECL clock
input. The outputs are configurable and support 1:1 and 1:2
output to input frequency ratios. The ASM2I99456 is
specified for the extended temperature range of –40 to
85°C.
The ASM2I99456 is a full static design supporting clock
frequencies up to 250 MHz. The signals are generated and
retimed on-chip to ensure minimal skew between the three
output banks.
Each of the three output banks can be individually supplied
by 2.5V or 3.3V supporting mixed voltage applications. The
FSELx pins choose between division of the input reference
frequency by one or two. The frequency divider can be set
individually for each of the three output banks. The
ASM2I99456 can be reset and the outputs are disabled by
deasserting the MR/OE pin (logic high state). Asserting
MR/OE will enable the outputs.
All control inputs accept LVCMOS signals while the outputs
provide LVCMOS compatible levels with the capability to
drive terminated 50Ω transmission lines. The clock input is
low voltage PECL compatible for differential clock
distribution support. Please consult the ASM2I99446
specification for a full CMOS compatible device. For series
terminated transmission lines, each of the ASM2I99456
outputs can drive one or two traces giving the devices an
effective fanout of 1:20. The device is packaged in a
7x7 mm
2
32-lead LQFP and TQFP Packages.