June 2005 ASM2P20805A

rev 0.2


Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
2.5V CMOS Dual 1-To-5 Clock Driver

Features
ƒ Advanced CMOS Technology
ƒ Guaranteed low skew < 200pS (max.)
ƒ Very low propagation delay < 2.5nS (max)
ƒ Very low duty cycle distortion < 270pS (max)
ƒ Very low CMOS power levels
ƒ Operating frequency up to 166MHz
ƒ TTL compatible inputs and outputs
ƒ Two independent output banks with 3-state control
ƒ 1:5 fanout per bank
ƒ "Heartbeat" monitor output
ƒ V
CC
= 2.5V ± 0.2V
ƒ Available in SSOP and QSOP packages





Block Diagram


Functional Description
The ASM2P20805A is a 2.5V Clock driver built using
advanced CMOS technology. The device consists of two
banks of drivers, each with a 1:5 fanout and its own output
enable control. The device has a "heartbeat" monitor for
diagnostics and PLL driving. The MON output is identical to
all other outputs and complies with the output specifications
in this document. The ASM2P20805A offers low
capacitance inputs. The ASM2P20805A is designed for
high speed clock distribution where signal quality and skew
are critical. The ASM2P20805A also allows single point-to-
point transmission line driving in applications such as
address distribution, where one signal must be distributed
to multiple receivers with low skew and high signal quality.







Pin Diagram




OB
1
– OB
5

IN
A

IN
B

OE
B

OE
A

OA
1
– OA
5

MON
5
5
V
CCB

OB
1

OB
2

OB
3

GND
B

OB
4

OB
5

MON
OE
B

IN
B
IN
A

OE
A

GND
Q

OA
5

OA
4

GND
A

OA
3

OA
2

OA
1

V
CCA

A
S
M
2
P
2
0
8
0
5
A
10 11
9 12
8 13
7 14
6 15
5 16
4 17
3 18
2 19
1 20