January 2005
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C4098
AS7C34098
5V/3.3V 256K × 16 CMOS SRAM
1/13/05; v.1.9 Alliance Semiconductor P. 1 of 10
Features
• AS7C4098 (5V version)
• AS7C34098 (3.3V version)
• Industrial and commercial temperature
• Organization: 262,144 words × 16 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 1375 mW (AS7C4098)/max @ 12 ns
- 576 mW (AS7C34098)/max @ 10 ns
• Low power consumption: STANDBY
- 110 mW (AS7C4098)/max CMOS
- 72 mW (AS7C34098)/max CMOS
• Individual byte read/write controls
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
- 400-mil SOJ
- TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 100 mA
Logic block diagram
1024 × 256 × 16
Array
(4,194,304)
OE
CE
WE
Column decoder
Ro
w De
cod
e
r
A0
A1
A2
A3
A4
A6
A7
A8
V
CC
GND
A12
A5 A9
A10 A1
1
A14 A15 A16 A17
A13
Control circuit
I/O1–I/O8
I/O9–I/O16
UB
LB
I/O
buffer
Pin arrangement for SOJ and TSOP 2
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O14
I/O13
GND
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
A4
CE
I/O1
I/O2
I/O3
I/O4
V
CC
GND
I/O5
I/O6
I/O7
I/O8
WE
A5
A6
A7
TSOP2
21
22
A8
A9
UB
LB
I/O16
I/O15
2A1
3A2
4A3
1A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A16
A15
OE
A17
44-pin (400 mil) SOJ
Selection guide
–10 –12 –15 –20 Unit
Maximum address access time 10 12 15 20 ns
Maximum output enable access time 5 6 7 8 ns
Maximum operating current
AS7C4098 – 250 220 180 mA
AS7C34098 160 130 110 100 mA
Maximum CMOS standby current
AS7C4098 – 20 20 20 mA
AS7C34098 20 20 20 20 mA