August 2004
Copyright © Alliance Semiconductor. All rights reserved.
AS7C34096A
3.3V 512K × 8 CMOS SRAM
®
8/17/04, v. 2.1 Alliance Semiconductor P. 1 of 9
Features
• Pin compatible to AS7C34096
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
• Low power consumption: ACTIVE
- 650 mW / max @ 10 ns
• Low power consumption: STANDBY
- 28.8 mW / max CMOS
• Equal access and cycle times
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
524,288 × 8
Array
(4,194,304)
Se
ns
e a
m
p
Input buffer
I/O8
I/O1
OE
CE
WEColumn decoder
R
o
w decoder
Control
Circuit
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
A1
0
A1
1
A1
2
A1
3
A1
4
A1
5
A1
6
A1
7
A1
8
A9
Pin arrangements
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A15
OE
I/O8
I/O7
GND
V
CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
A0
A1
A2
A3
A4
CE
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A5
A6
A7
17
18
A8
A9
36
35
34
33
NC
A18
A17
A16
GND
V
CC
I/O6
I/O5
NC
A14
A13
A12
A11
A10
A4
CE
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
I/O8
I/O7
A1
A2
A3
A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A16
A15
A175
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2
3
4
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
OE
A18
36-pin SOJ (400 mil)
44-pin TSOP 2
Selection guide
–10 –12 –15 –20 Unit
Maximum address access time 10 12 15 20 ns
Maximum outputenable access time 4 5 6 7 ns
Maximum operating current
Industrial 180 160 140 110 mA
Commercial 170 150 130 100 mA
Maximum CMOS standby current 8 8 8 8 mA