April 2005
Copyright © Alliance Semiconductor. All rights reserved.
®
AS7C3364NTF32B
AS7C3364NTF36B
4/28/05, v 1.0 Alliance Semiconductor P. 1 of 19
3.3V 64K × 32/36 Flowthrough Synchronous SRAM with NTD
TM
Features
• Organization: 65,536 words × 32 or 36 bits
•NTD
™
architecture for efficient bus operation
• Fast clock to data access: 7.5/8.0/10.0 ns
•Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
Selection guide
-75 -80 -10 Units
Minimum cycle time 8.5 10 12 ns
Maximum clock access time 7.5 8.0 10 ns
Maximum operating current 260 230 200 mA
Maximum standby current 110 100 90 mA
Maximum CMOS standby current (DC) 30 30 30 mA
W
r
ite Buf
fe
r
Address
D Q
CLK
register
Output
Buffer
DQ[a,b,c,d]
16
16
CLK
CE0
CE1
CE2
A[15:0]
OE
CEN
Control
CLK
logic
Data
D
Q
CLK
Input
Register
32/36
32/36
OE
64K x 32/36
SRAM
Array
R/W
DQ[a,b,c,d]
BWb
BWd
CLK
QD
ADV / LD
LBO
Burst logic
addr. registers
Write delay
16
ZZ
CLK
32/36 32/36
32/36
32/36
BWc
BWa