February 2005
Copyright © Alliance Semiconductor. All rights reserved.
AS7C3364FT32B
3.3V 64K × 32/36 Flow Through Synchronous SRAM
®
2/8/05; v.1.2 Alliance Semiconductor P. 1 of 19
AS7C3364FT36B
Features
• Organization: 65,536 words × 32 or 36 bits
• Fast clock to data access: 6.5/7.5/8.0/10.0 ns
•Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and Global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• Linear or interleaved burst control
• Snooze mode for reduced power standby
• Common data inputs and data outputs
Selection guide
–65 -75 -80 -10 Units
Minimum cycle time 7.5 8.5 10 12 ns
Maximum clock access time 6.5 7.5 8.0 10.0 ns
Maximum operating current 275 250 215 185 mA
Maximum standby current 90 85 75 75 mA
Maximum CMOS standby current (DC) 30 30 30 30 mA
Logic block diagram
Q0
Q1
64K × 32/36
Memory
array
Burst logic
CLK
CLR
CE
Address
DQ
CE
CLK
DQ
d
CLK
DQ
Byte write
registers
register
DQ
c
CLK
DQ
Byte write
registers
DQ
b
CLK
DQ
Byte write
registers
DQ
a
CLK
DQ
Byte write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
buffer
Input
registers
Power
down
DQ[a:d]
4
36/32
181618
18
GWE
BWE
BW
d
ADV
ADSC
ADSP
CLK
CE0
CE1
CE2
BW
c
BW
b
BW
a
OE
ZZ
LBO
OE
CLK
36/32
36/32
A[17:0]