December 2004
Copyright © Alliance Semiconductor. All rights reserved.
®
12/23/04, v 1.3 Alliance Semiconductor 1 of 19
3.3V 2M × 18 Flow-through synchronous SRAM
AS7C332MFT18A
Features
• Organization: 2,097152 words × 18 bits
• Fast clock to data access: 7.5/8.5/10 ns
•Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V
DDQ
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
Selection guide
-75 -85 -10 Units
Minimum cycle time 8.5 10 12 ns
Maximum clock access time 7.5 8.5 10 ns
Maximum operating current 325 300 275 mA
Maximum standby current 140 130 130 mA
Maximum CMOS standby current (DC) 90 90 90 mA
Burst logic
ADV
ADSC
ADSP
CLK
LBO
CLK
CLR
CS
211921
A[20:0]
21
Address
D Q
CS
CLK
register
2M x 18
Memory
array
1818
DQb
CLK
DQ
Byte Write
registers
DQa
CLK
DQ
Byte Write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
registers
Input
registers
Power
down
DQ[a,b]
2
CE0
CE1
CE2
BW
b
BW
a
OE
ZZ
OE
CLK
CLK

BWE
GWE
18